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Searched refs:SRII (Results 1 – 25 of 30) sorted by relevance

12

/linux/drivers/gpu/drm/amd/display/dc/dce/
H A Ddce_clock_source.h60 SRII(PHASE, DP_DTO, 0),\
61 SRII(PHASE, DP_DTO, 1),\
62 SRII(PHASE, DP_DTO, 2),\
63 SRII(PHASE, DP_DTO, 3),\
64 SRII(PHASE, DP_DTO, 4),\
65 SRII(PHASE, DP_DTO, 5),\
66 SRII(MODULO, DP_DTO, 0),\
67 SRII(MODULO, DP_DTO, 1),\
68 SRII(MODULO, DP_DTO, 2),\
69 SRII(MODULO, DP_DTO, 3),\
[all …]
/linux/drivers/gpu/drm/amd/display/dc/mpc/dcn32/
H A Ddcn32_mpc.h36 SRII(MPCC_MOVABLE_CM_LOCATION_CONTROL, MPCC, inst),\
37 SRII(MPCC_MCM_SHAPER_CONTROL, MPCC_MCM, inst),\
38 SRII(MPCC_MCM_SHAPER_OFFSET_R, MPCC_MCM, inst),\
39 SRII(MPCC_MCM_SHAPER_OFFSET_G, MPCC_MCM, inst),\
40 SRII(MPCC_MCM_SHAPER_OFFSET_B, MPCC_MCM, inst),\
41 SRII(MPCC_MCM_SHAPER_SCALE_R, MPCC_MCM, inst),\
42 SRII(MPCC_MCM_SHAPER_SCALE_G_B, MPCC_MCM, inst),\
43 SRII(MPCC_MCM_SHAPER_LUT_INDEX, MPCC_MCM, inst),\
44 SRII(MPCC_MCM_SHAPER_LUT_DATA, MPCC_MCM, inst),\
45 SRII(MPCC_MCM_SHAPER_LUT_WRITE_EN_MASK, MPCC_MCM, inst),\
[all …]
/linux/drivers/gpu/drm/amd/display/dc/resource/dcn32/
H A Ddcn32_resource.h777 SRII(MUX, MPC_OUT, inst), VUPDATE_SRII(CUR, VUPDATE_LOCK_SET, inst)
780 MPC_OUT_MUX_COMMON_REG_LIST_DCN1_0_RI(inst), SRII(CSC_MODE, MPC_OUT, inst), \
781 SRII(CSC_C11_C12_A, MPC_OUT, inst), SRII(CSC_C33_C34_A, MPC_OUT, inst), \
782 SRII(CSC_C11_C12_B, MPC_OUT, inst), SRII(CSC_C33_C34_B, MPC_OUT, inst), \
783 SRII(DENORM_CONTROL, MPC_OUT, inst), \
784 SRII(DENORM_CLAMP_G_Y, MPC_OUT, inst), \
785 SRII(DENORM_CLAMP_B_CB, MPC_OUT, inst), SR(MPC_OUT_CSC_COEF_FORMAT)
788 SRII(MPCC_TOP_SEL, MPCC, inst), SRII(MPCC_BOT_SEL, MPCC, inst), \
789 SRII(MPCC_CONTROL, MPCC, inst), SRII(MPCC_STATUS, MPCC, inst), \
790 SRII(MPCC_OPP_ID, MPCC, inst), SRII(MPCC_BG_G_Y, MPCC, inst), \
[all …]
H A Ddcn32_resource.c155 #define SRII(reg_name, block, id)\ macro
539 SRII(PIXEL_RATE_CNTL, OTG, 0), \
540 SRII(PIXEL_RATE_CNTL, OTG, 1),\
541 SRII(PIXEL_RATE_CNTL, OTG, 2),\
542 SRII(PIXEL_RATE_CNTL, OTG, 3),\
543 SRII(PHYPLL_PIXEL_RATE_CNTL, OTG, 0),\
544 SRII(PHYPLL_PIXEL_RATE_CNTL, OTG, 1),\
545 SRII(PHYPLL_PIXEL_RATE_CNTL, OTG, 2),\
546 SRII(PHYPLL_PIXEL_RATE_CNTL, OTG, 3),\
/linux/drivers/gpu/drm/amd/display/dc/mpc/dcn20/
H A Ddcn20_mpc.h35 SRII(MPCC_TOP_GAIN, MPCC, inst),\
36 SRII(MPCC_BOT_GAIN_INSIDE, MPCC, inst),\
37 SRII(MPCC_BOT_GAIN_OUTSIDE, MPCC, inst),\
38 SRII(MPCC_OGAM_RAMA_START_CNTL_B, MPCC_OGAM, inst),\
39 SRII(MPCC_OGAM_RAMA_START_CNTL_G, MPCC_OGAM, inst),\
40 SRII(MPCC_OGAM_RAMA_START_CNTL_R, MPCC_OGAM, inst),\
41 SRII(MPCC_OGAM_RAMA_SLOPE_CNTL_B, MPCC_OGAM, inst),\
42 SRII(MPCC_OGAM_RAMA_SLOPE_CNTL_G, MPCC_OGAM, inst),\
43 SRII(MPCC_OGAM_RAMA_SLOPE_CNTL_R, MPCC_OGAM, inst),\
44 SRII(MPCC_OGAM_RAMA_END_CNTL1_B, MPCC_OGAM, inst),\
[all …]
/linux/drivers/gpu/drm/amd/display/dc/mpc/dcn401/
H A Ddcn401_mpc.h108 SRII(MPCC_MCM_FIRST_GAMUT_REMAP_COEF_FORMAT, MPCC_MCM, inst),\
109 SRII(MPCC_MCM_FIRST_GAMUT_REMAP_MODE, MPCC_MCM, inst),\
110 SRII(MPC_MCM_FIRST_GAMUT_REMAP_C11_C12_A, MPCC_MCM, inst),\
111 SRII(MPC_MCM_FIRST_GAMUT_REMAP_C13_C14_A, MPCC_MCM, inst),\
112 SRII(MPC_MCM_FIRST_GAMUT_REMAP_C21_C22_A, MPCC_MCM, inst),\
113 SRII(MPC_MCM_FIRST_GAMUT_REMAP_C23_C24_A, MPCC_MCM, inst),\
114 SRII(MPC_MCM_FIRST_GAMUT_REMAP_C31_C32_A, MPCC_MCM, inst),\
115 SRII(MPC_MCM_FIRST_GAMUT_REMAP_C33_C34_A, MPCC_MCM, inst),\
116 SRII(MPC_MCM_FIRST_GAMUT_REMAP_C11_C12_B, MPCC_MCM, inst),\
117 SRII(MPC_MCM_FIRST_GAMUT_REMAP_C13_C14_B, MPCC_MCM, inst),\
[all …]
/linux/drivers/gpu/drm/amd/display/dc/mpc/dcn30/
H A Ddcn30_mpc.h47 SRII(MPCC_TOP_GAIN, MPCC, inst),\
48 SRII(MPCC_BOT_GAIN_INSIDE, MPCC, inst),\
49 SRII(MPCC_BOT_GAIN_OUTSIDE, MPCC, inst),\
50 SRII(MPCC_MEM_PWR_CTRL, MPCC, inst),\
51 SRII(MPCC_OGAM_LUT_INDEX, MPCC_OGAM, inst),\
52 SRII(MPCC_OGAM_LUT_DATA, MPCC_OGAM, inst), \
53 SRII(MPCC_GAMUT_REMAP_COEF_FORMAT, MPCC_OGAM, inst),\
54 SRII(MPCC_GAMUT_REMAP_MODE, MPCC_OGAM, inst),\
55 SRII(MPC_GAMUT_REMAP_C11_C12_A, MPCC_OGAM, inst),\
56 SRII(MPC_GAMUT_REMAP_C33_C34_A, MPCC_OGAM, inst),\
[all …]
/linux/drivers/gpu/drm/amd/display/dc/hwss/dce/
H A Ddce_hwseq.h39 SRII(DCFE_CLOCK_CONTROL, DCFE, 0), \
40 SRII(DCFE_CLOCK_CONTROL, DCFE, 1), \
41 SRII(DCFE_CLOCK_CONTROL, DCFE, 2), \
42 SRII(DCFE_CLOCK_CONTROL, DCFE, 3), \
43 SRII(DCFE_CLOCK_CONTROL, DCFE, 4), \
44 SRII(DCFE_CLOCK_CONTROL, DCFE, 5), \
48 SRII(BLND_V_UPDATE_LOCK, BLND, 0), \
49 SRII(BLND_V_UPDATE_LOCK, BLND, 1), \
50 SRII(BLND_V_UPDATE_LOCK, BLND, 2), \
51 SRII(BLND_V_UPDATE_LOCK, BLND, 3), \
[all …]
/linux/drivers/gpu/drm/amd/display/dc/mpc/dcn10/
H A Ddcn10_mpc.h34 SRII(MPCC_TOP_SEL, MPCC, inst),\
35 SRII(MPCC_BOT_SEL, MPCC, inst),\
36 SRII(MPCC_CONTROL, MPCC, inst),\
37 SRII(MPCC_STATUS, MPCC, inst),\
38 SRII(MPCC_OPP_ID, MPCC, inst),\
39 SRII(MPCC_BG_G_Y, MPCC, inst),\
40 SRII(MPCC_BG_R_CR, MPCC, inst),\
41 SRII(MPCC_BG_B_CB, MPCC, inst),\
42 SRII(MPCC_SM_CONTROL, MPCC, inst),\
43 SRII(MPCC_UPDATE_LOCK_SEL, MPCC, inst)
[all …]
/linux/drivers/gpu/drm/amd/display/dc/resource/dcn35/
H A Ddcn35_resource.h174 SRII(PIXEL_RATE_CNTL, OTG, 0), \
175 SRII(PIXEL_RATE_CNTL, OTG, 1),\
176 SRII(PIXEL_RATE_CNTL, OTG, 2),\
177 SRII(PIXEL_RATE_CNTL, OTG, 3),\
178 SRII(PHYPLL_PIXEL_RATE_CNTL, OTG, 0),\
179 SRII(PHYPLL_PIXEL_RATE_CNTL, OTG, 1),\
180 SRII(PHYPLL_PIXEL_RATE_CNTL, OTG, 2),\
181 SRII(PHYPLL_PIXEL_RATE_CNTL, OTG, 3),\
/linux/drivers/gpu/drm/amd/display/dc/resource/dcn316/
H A Ddcn316_resource.c164 #define SRII(reg_name, block, id)\ macro
683 SRII(PIXEL_RATE_CNTL, OTG, 0), \
684 SRII(PIXEL_RATE_CNTL, OTG, 1),\
685 SRII(PIXEL_RATE_CNTL, OTG, 2),\
686 SRII(PIXEL_RATE_CNTL, OTG, 3),\
687 SRII(PHYPLL_PIXEL_RATE_CNTL, OTG, 0),\
688 SRII(PHYPLL_PIXEL_RATE_CNTL, OTG, 1),\
689 SRII(PHYPLL_PIXEL_RATE_CNTL, OTG, 2),\
690 SRII(PHYPLL_PIXEL_RATE_CNTL, OTG, 3),\
/linux/drivers/gpu/drm/amd/display/dc/resource/dcn314/
H A Ddcn314_resource.c161 #define SRII(reg_name, block, id)\ macro
696 SRII(PIXEL_RATE_CNTL, OTG, 0), \
697 SRII(PIXEL_RATE_CNTL, OTG, 1),\
698 SRII(PIXEL_RATE_CNTL, OTG, 2),\
699 SRII(PIXEL_RATE_CNTL, OTG, 3),\
700 SRII(PHYPLL_PIXEL_RATE_CNTL, OTG, 0),\
701 SRII(PHYPLL_PIXEL_RATE_CNTL, OTG, 1),\
702 SRII(PHYPLL_PIXEL_RATE_CNTL, OTG, 2),\
703 SRII(PHYPLL_PIXEL_RATE_CNTL, OTG, 3),\
/linux/drivers/gpu/drm/amd/display/dc/resource/dcn31/
H A Ddcn31_resource.c144 #define SRII(reg_name, block, id)\ macro
689 SRII(PIXEL_RATE_CNTL, OTG, 0), \
690 SRII(PIXEL_RATE_CNTL, OTG, 1),\
691 SRII(PIXEL_RATE_CNTL, OTG, 2),\
692 SRII(PIXEL_RATE_CNTL, OTG, 3),\
693 SRII(PHYPLL_PIXEL_RATE_CNTL, OTG, 0),\
694 SRII(PHYPLL_PIXEL_RATE_CNTL, OTG, 1),\
695 SRII(PHYPLL_PIXEL_RATE_CNTL, OTG, 2),\
696 SRII(PHYPLL_PIXEL_RATE_CNTL, OTG, 3),\
/linux/drivers/gpu/drm/amd/display/dc/resource/dcn321/
H A Ddcn321_resource.c156 #define SRII(reg_name, block, id)\ macro
536 SRII(PIXEL_RATE_CNTL, OTG, 0), \
537 SRII(PIXEL_RATE_CNTL, OTG, 1),\
538 SRII(PIXEL_RATE_CNTL, OTG, 2),\
539 SRII(PIXEL_RATE_CNTL, OTG, 3),\
540 SRII(PHYPLL_PIXEL_RATE_CNTL, OTG, 0),\
541 SRII(PHYPLL_PIXEL_RATE_CNTL, OTG, 1),\
542 SRII(PHYPLL_PIXEL_RATE_CNTL, OTG, 2),\
543 SRII(PHYPLL_PIXEL_RATE_CNTL, OTG, 3),\
/linux/drivers/gpu/drm/amd/display/dc/resource/dcn315/
H A Ddcn315_resource.c178 #define SRII(reg_name, block, id)\ macro
688 SRII(PIXEL_RATE_CNTL, OTG, 0), \
689 SRII(PIXEL_RATE_CNTL, OTG, 1),\
690 SRII(PIXEL_RATE_CNTL, OTG, 2),\
691 SRII(PIXEL_RATE_CNTL, OTG, 3),\
692 SRII(PHYPLL_PIXEL_RATE_CNTL, OTG, 0),\
693 SRII(PHYPLL_PIXEL_RATE_CNTL, OTG, 1),\
694 SRII(PHYPLL_PIXEL_RATE_CNTL, OTG, 2),\
695 SRII(PHYPLL_PIXEL_RATE_CNTL, OTG, 3),\
/linux/drivers/gpu/drm/amd/display/dc/resource/dcn401/
H A Ddcn401_resource.c147 #define SRII(reg_name, block, id)\ macro
519 SRII(PIXEL_RATE_CNTL, OTG, 0), \
520 SRII(PIXEL_RATE_CNTL, OTG, 1),\
521 SRII(PIXEL_RATE_CNTL, OTG, 2),\
522 SRII(PIXEL_RATE_CNTL, OTG, 3),\
523 SRII(PHYPLL_PIXEL_RATE_CNTL, OTG, 0),\
524 SRII(PHYPLL_PIXEL_RATE_CNTL, OTG, 1),\
525 SRII(PHYPLL_PIXEL_RATE_CNTL, OTG, 2),\
526 SRII(PHYPLL_PIXEL_RATE_CNTL, OTG, 3),\
/linux/drivers/gpu/drm/amd/display/dc/hpo/dcn31/
H A Ddcn31_hpo_dp_link_encoder.h68 SRII(RDPCSTX_PHY_CNTL6, RDPCSTX, id)
/linux/drivers/gpu/drm/amd/display/dc/dcn10/
H A Ddcn10_dwb.h43 #define SRII(reg_name, block, id)\ macro
/linux/drivers/gpu/drm/amd/display/dc/resource/dcn201/
H A Ddcn201_resource.c263 #define SRII(reg_name, block, id)\ macro
/linux/drivers/gpu/drm/amd/display/dc/resource/dce112/
H A Ddce112_resource.c521 #define SRII(reg_name, block, id)\ macro
/linux/drivers/gpu/drm/amd/display/dc/resource/dce110/
H A Ddce110_resource.c540 #define SRII(reg_name, block, id)\ macro
/linux/drivers/gpu/drm/amd/display/dc/resource/dcn302/
H A Ddcn302_resource.c187 #define SRII(reg_name, block, id)\ macro
/linux/drivers/gpu/drm/amd/display/dc/resource/dcn303/
H A Ddcn303_resource.c184 #define SRII(reg_name, block, id)\ macro
/linux/drivers/gpu/drm/amd/display/dc/resource/dcn10/
H A Ddcn10_resource.c120 #define SRII(reg_name, block, id)\ macro
/linux/drivers/gpu/drm/amd/display/dc/resource/dcn301/
H A Ddcn301_resource.c132 #define SRII(reg_name, block, id)\ macro

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