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Searched refs:SR (Results 1 – 25 of 145) sorted by relevance

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/linux/drivers/gpu/drm/amd/display/dc/dce/
H A Ddce_dmcu.h33 SR(DMCU_CTRL), \
34 SR(DMCU_STATUS), \
35 SR(DMCU_RAM_ACCESS_CTRL), \
36 SR(DMCU_IRAM_WR_CTRL), \
37 SR(DMCU_IRAM_WR_DATA), \
38 SR(MASTER_COMM_DATA_REG1), \
39 SR(MASTER_COMM_DATA_REG2), \
40 SR(MASTER_COMM_DATA_REG3), \
41 SR(MASTER_COMM_CMD_REG), \
42 SR(MASTER_COMM_CNTL_REG), \
[all …]
H A Ddce_abm.h33 SR(MASTER_COMM_CNTL_REG), \
34 SR(MASTER_COMM_CMD_REG), \
35 SR(MASTER_COMM_DATA_REG1)
39 SR(DC_ABM1_HG_SAMPLE_RATE), \
40 SR(DC_ABM1_LS_SAMPLE_RATE), \
41 SR(BL1_PWM_BL_UPDATE_SAMPLE_RATE), \
42 SR(DC_ABM1_HG_MISC_CTRL), \
43 SR(DC_ABM1_IPCSC_COEFF_SEL), \
44 SR(BL1_PWM_CURRENT_ABM_LEVEL), \
45 SR(BL1_PWM_TARGET_ABM_LEVEL), \
[all …]
H A Ddce_panel_cntl.h39 SR(BL_PWM_CNTL), \
40 SR(BL_PWM_CNTL2), \
41 SR(BL_PWM_PERIOD_CNTL), \
42 SR(BL_PWM_GRP1_REG_LOCK), \
43 SR(BIOS_SCRATCH_2)
53 SR(BL_PWM_CNTL), \
54 SR(BL_PWM_CNTL2), \
55 SR(BL_PWM_PERIOD_CNTL), \
56 SR(BL_PWM_GRP1_REG_LOCK), \
H A Ddce_link_encoder.h48 SR(DMCU_RAM_ACCESS_CTRL), \
49 SR(DMCU_IRAM_RD_CTRL), \
50 SR(DMCU_IRAM_RD_DATA), \
51 SR(DMCU_INTERRUPT_TO_UC_EN_MASK), \
77 SR(DCI_MEM_PWR_STATUS)
82 SR(DMCU_RAM_ACCESS_CTRL), \
83 SR(DMCU_IRAM_RD_CTRL), \
84 SR(DMCU_IRAM_RD_DATA), \
85 SR(DMCU_INTERRUPT_TO_UC_EN_MASK), \
110 SR(DAC_ENABLE)
[all …]
H A Ddce_audio.h33 SR(AZALIA_F0_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS),\
34 SR(AZALIA_F0_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES),\
35 SR(AZALIA_F0_CODEC_FUNCTION_PARAMETER_POWER_STATES),\
36 SR(DCCG_AUDIO_DTO_SOURCE),\
37 SR(DCCG_AUDIO_DTO0_MODULE),\
38 SR(DCCG_AUDIO_DTO0_PHASE),\
39 SR(DCCG_AUDIO_DTO1_MODULE),\
40 SR(DCCG_AUDIO_DTO1_PHASE)
H A Ddce_i2c_hw.h88 SR(DC_I2C_ARBITRATION),\
89 SR(DC_I2C_CONTROL),\
90 SR(DC_I2C_SW_STATUS),\
91 SR(DC_I2C_TRANSACTION0),\
92 SR(DC_I2C_TRANSACTION1),\
93 SR(DC_I2C_TRANSACTION2),\
94 SR(DC_I2C_TRANSACTION3),\
95 SR(DC_I2C_DATA),\
96 SR(MICROSECOND_TIME_BASE_DIV)
100 SR(DIO_MEM_PWR_CTRL),\
[all …]
/linux/drivers/gpu/drm/amd/display/dc/dwb/dcn30/
H A Ddcn30_dwb.h31 SR(DWB_ENABLE_CLK_CTRL),\
32 SR(DWB_MEM_PWR_CTRL),\
33 SR(FC_MODE_CTRL),\
34 SR(FC_FLOW_CTRL),\
35 SR(FC_WINDOW_START),\
36 SR(FC_WINDOW_SIZE),\
37 SR(FC_SOURCE_SIZE),\
38 SR(DWB_UPDATE_CTRL),\
39 SR(DWB_CRC_CTRL),\
40 SR(DWB_CRC_MASK_R_G),\
[all …]
/linux/drivers/gpu/drm/amd/display/dc/hubbub/dcn31/
H A Ddcn31_hubbub.h33 SR(DCHVM_CTRL0),\
34 SR(DCHVM_MEM_CTRL),\
35 SR(DCHVM_CLK_CTRL),\
36 SR(DCHVM_RIOMMU_CTRL0),\
37 SR(DCHVM_RIOMMU_STAT0),\
38 SR(DCHUBBUB_DET0_CTRL),\
39 SR(DCHUBBUB_DET1_CTRL),\
40 SR(DCHUBBUB_DET2_CTRL),\
41 SR(DCHUBBUB_DET3_CTRL),\
42 SR(DCHUBBUB_COMPBUF_CTRL),\
[all …]
/linux/drivers/gpu/drm/amd/display/dc/pg/dcn35/
H A Ddcn35_pg_cntl.h33 SR(DOMAIN0_PG_CONFIG), \
34 SR(DOMAIN1_PG_CONFIG), \
35 SR(DOMAIN2_PG_CONFIG), \
36 SR(DOMAIN3_PG_CONFIG), \
37 SR(DOMAIN16_PG_CONFIG), \
38 SR(DOMAIN17_PG_CONFIG), \
39 SR(DOMAIN18_PG_CONFIG), \
40 SR(DOMAIN19_PG_CONFIG), \
41 SR(DOMAIN22_PG_CONFIG), \
42 SR(DOMAIN23_PG_CONFIG), \
[all …]
/linux/drivers/gpu/drm/amd/display/dc/hubbub/dcn21/
H A Ddcn21_hubbub.h31 SR(DCHUBBUB_ARB_FRAC_URG_BW_NOM_A),\
32 SR(DCHUBBUB_ARB_FRAC_URG_BW_NOM_B),\
33 SR(DCHUBBUB_ARB_FRAC_URG_BW_NOM_C),\
34 SR(DCHUBBUB_ARB_FRAC_URG_BW_NOM_D),\
35 SR(DCHUBBUB_ARB_FRAC_URG_BW_FLIP_A),\
36 SR(DCHUBBUB_ARB_FRAC_URG_BW_FLIP_B),\
37 SR(DCHUBBUB_ARB_FRAC_URG_BW_FLIP_C),\
38 SR(DCHUBBUB_ARB_FRAC_URG_BW_FLIP_D),\
39 SR(DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_A),\
40 SR(DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_B),\
[all …]
/linux/Documentation/translations/zh_CN/PCI/
H A Dpci-iov-howto.rst28 什么是SR-IOV
31 单根I/O虚拟化（SR-IOV）是一种PCI Express扩展功能，它使一个物理设备显示为多个
42 我怎样才能启用SR-IOV功能
45 有多种方法可用于SR-IOV的启用。在第一种方法中，设备驱动（PF驱动）将通过SR-IOV
46 核心提供的API控制功能的启用和禁用。如果硬件具有SR-IOV能力，加载其PF驱动器将启
63 SR-IOV API
66 用来开启SR-IOV功能:
79 用来关闭SR-IOV功能:
90 要想通过主机上的兼容驱动启用自动探测VF，在启用SR-IOV功能之前运行下面的命令。这
97 要禁止主机上的兼容驱动自动探测VF，请在启用SR-IOV功能之前运行以下命令。更新这个
[all …]
/linux/tools/testing/selftests/kvm/arm64/
H A Dvgic_init.c769 #define SR(r) \ macro
776 SR(SYS_ICC_PMR_EL1),
777 SR(SYS_ICC_BPR0_EL1),
778 SR(SYS_ICC_AP0R0_EL1),
779 SR(SYS_ICC_AP0R1_EL1),
780 SR(SYS_ICC_AP0R2_EL1),
781 SR(SYS_ICC_AP0R3_EL1),
782 SR(SYS_ICC_AP1R0_EL1),
783 SR(SYS_ICC_AP1R1_EL1),
784 SR(SYS_ICC_AP1R2_EL
[all...]
/linux/Documentation/networking/
H A Dseg6-sysctl.rst12 Accept or drop SR-enabled IPv6 packets on this interface.
20 Define HMAC policy for ingress SR-enabled packets on this interface.
23 * 0 - Accept SR packets without HMAC, validate SR packets with HMAC
24 * 1 - Drop SR packets without HMAC, validate SR packets with HMAC
33 IPv6 header in case of SR T.encaps
/linux/Documentation/PCI/
H A Dpci-iov-howto.rst15 What is SR-IOV
18 Single Root I/O Virtualization (SR-IOV) is a PCI Express Extended
34 How can I enable SR-IOV capability
37 Multiple methods are available for SR-IOV enablement.
39 enabling and disabling of the capability via API provided by SR-IOV core.
40 If the hardware has SR-IOV capability, loading its PF driver would
63 SR-IOV API
66 To enable SR-IOV capability:
79 To disable SR-IOV capability:
91 command below before enabling SR-IOV capabilities. This is the
[all …]
/linux/drivers/gpu/drm/amd/display/dc/resource/dcn316/
H A Ddcn316_resource.c148 #define SR(reg_name)\ macro
673 SR(DCHUBBUB_GLOBAL_TIMER_CNTL), \
674 SR(DCHUBBUB_ARB_HOSTVM_CNTL), \
675 SR(DIO_MEM_PWR_CTRL), \
676 SR(ODM_MEM_PWR_CTRL3), \
677 SR(DMU_MEM_PWR_CNTL), \
678 SR(MMHUBBUB_MEM_PWR_CNTL), \
679 SR(DCCG_GATE_DISABLE_CNTL), \
680 SR(DCCG_GATE_DISABLE_CNTL2), \
681 SR(DCFCLK_CNTL),\
[all …]
/linux/drivers/gpu/drm/amd/display/dc/resource/dcn314/
H A Ddcn314_resource.c145 #define SR(reg_name)\ macro
686 SR(DCHUBBUB_GLOBAL_TIMER_CNTL), \
687 SR(DCHUBBUB_ARB_HOSTVM_CNTL), \
688 SR(DIO_MEM_PWR_CTRL), \
689 SR(ODM_MEM_PWR_CTRL3), \
690 SR(DMU_MEM_PWR_CNTL), \
691 SR(MMHUBBUB_MEM_PWR_CNTL), \
692 SR(DCCG_GATE_DISABLE_CNTL), \
693 SR(DCCG_GATE_DISABLE_CNTL2), \
694 SR(DCFCLK_CNTL),\
[all …]
/linux/drivers/macintosh/
H A Dvia-cuda.c50 #define SR (10*RS) /* Shift register */ macro
343 (void)in_8(&via[SR]); in sync_egret()
358 (void)in_8(&via[SR]); in sync_egret()
386 (void)in_8(&via[SR]); /* clear any left-over data */ in cuda_init_via()
395 (void)in_8(&via[SR]); in cuda_init_via()
406 (void)in_8(&via[SR]); in cuda_init_via()
415 (void)in_8(&via[SR]); in cuda_init_via()
543 out_8(&via[SR], current_req->data[data_index++]); in cuda_start()
596 (void)in_8(&via[SR]); in cuda_interrupt()
606 (void)in_8(&via[SR]); in cuda_interrupt()
[all …]
H A Dvia-macii.c51 #define SR (10*RS) /* Shift register */ macro
173 x = via[SR]; in macii_init_via()
336 via[SR] = req->data[1]; in macii_start()
395 x = via[SR]; in macii_interrupt()
445 x = via[SR]; in macii_interrupt()
458 x = via[SR]; in macii_interrupt()
468 x = via[SR]; in macii_interrupt()
484 via[SR] = req->data[data_index++]; in macii_interrupt()
497 x = via[SR]; in macii_interrupt()
552 x = via[SR]; in macii_interrupt()
/linux/arch/alpha/math-emu/
H A Dmath.c101 FP_DECL_S(SA); FP_DECL_S(SB); FP_DECL_S(SR); in alpha_fp_emul()
135 FP_SUB_S(SR, SA, SB); in alpha_fp_emul()
139 FP_ADD_S(SR, SA, SB); in alpha_fp_emul()
143 FP_MUL_S(SR, SA, SB); in alpha_fp_emul()
147 FP_DIV_S(SR, SA, SB); in alpha_fp_emul()
151 FP_SQRT_S(SR, SB); in alpha_fp_emul()
221 FP_CONV(S,D,1,1,SR,DB); in alpha_fp_emul()
259 FP_FROM_INT_S(SR, ((long)vb), 64, long); in alpha_fp_emul()
271 FP_PACK_SP(&vc, SR); in alpha_fp_emul()
/linux/drivers/gpu/drm/amd/display/dc/resource/dcn315/
H A Ddcn315_resource.c162 #define SR(reg_name)\ macro
678 SR(DCHUBBUB_GLOBAL_TIMER_CNTL), \
679 SR(DCHUBBUB_ARB_HOSTVM_CNTL), \
680 SR(DIO_MEM_PWR_CTRL), \
681 SR(ODM_MEM_PWR_CTRL3), \
682 SR(DMU_MEM_PWR_CNTL), \
683 SR(MMHUBBUB_MEM_PWR_CNTL), \
684 SR(DCCG_GATE_DISABLE_CNTL), \
685 SR(DCCG_GATE_DISABLE_CNTL2), \
686 SR(DCFCLK_CNTL),\
[all …]
/linux/drivers/gpu/drm/amd/display/dc/resource/dcn31/
H A Ddcn31_resource.c128 #define SR(reg_name)\ macro
679 SR(DCHUBBUB_GLOBAL_TIMER_CNTL), \
680 SR(DCHUBBUB_ARB_HOSTVM_CNTL), \
681 SR(DIO_MEM_PWR_CTRL), \
682 SR(ODM_MEM_PWR_CTRL3), \
683 SR(DMU_MEM_PWR_CNTL), \
684 SR(MMHUBBUB_MEM_PWR_CNTL), \
685 SR(DCCG_GATE_DISABLE_CNTL), \
686 SR(DCCG_GATE_DISABLE_CNTL2), \
687 SR(DCFCLK_CNTL),\
[all …]
/linux/drivers/gpu/drm/amd/display/dc/resource/dcn321/
H A Ddcn321_resource.c117 #define SR(reg_name)\ macro
528 SR(DCHUBBUB_GLOBAL_TIMER_CNTL), \
529 SR(DIO_MEM_PWR_CTRL), \
530 SR(ODM_MEM_PWR_CTRL3), \
531 SR(MMHUBBUB_MEM_PWR_CNTL), \
532 SR(DCCG_GATE_DISABLE_CNTL), \
533 SR(DCCG_GATE_DISABLE_CNTL2), \
534 SR(DCFCLK_CNTL),\
535 SR(DC_MEM_GLOBAL_PWR_REQ_CNTL), \
544 SR(MICROSECOND_TIME_BASE_DIV), \
[all …]
/linux/arch/sparc/math-emu/
H A Dmath_32.c286 FP_DECL_S(SA); FP_DECL_S(SB); FP_DECL_S(SR); in do_one_mathemu()
428 case FADDS: FP_ADD_S (SR, SA, SB); break; in do_one_mathemu()
432 case FSUBS: FP_SUB_S (SR, SA, SB); break; in do_one_mathemu()
436 case FMULS: FP_MUL_S (SR, SA, SB); break; in do_one_mathemu()
444 case FDIVS: FP_DIV_S (SR, SA, SB); break; in do_one_mathemu()
448 case FSQRTS: FP_SQRT_S (SR, SB); break; in do_one_mathemu()
460 case FITOS: IR = rs2->s; FP_FROM_INT_S (SR, IR, 32, int); break; in do_one_mathemu()
467 case FDTOS: FP_CONV (S, D, 1, 2, SR, DB); break; in do_one_mathemu()
468 case FQTOS: FP_CONV (S, Q, 1, 4, SR, QB); break; in do_one_mathemu()
507 case 5: FP_PACK_SP (rd, SR); break; in do_one_mathemu()
H A Dmath_64.c181 FP_DECL_S(SA); FP_DECL_S(SB); FP_DECL_S(SR); in do_mathemu()
433 case FADDS: FP_ADD_S (SR, SA, SB); break; in do_mathemu()
437 case FSUBS: FP_SUB_S (SR, SA, SB); break; in do_mathemu()
441 case FMULS: FP_MUL_S (SR, SA, SB); break; in do_mathemu()
449 case FDIVS: FP_DIV_S (SR, SA, SB); break; in do_mathemu()
453 case FSQRTS: FP_SQRT_S (SR, SB); break; in do_mathemu()
471 case FXTOS: XR = rs2->d; FP_FROM_INT_S (SR, XR, 64, long); break; in do_mathemu()
474 case FITOS: IR = rs2->s; FP_FROM_INT_S (SR, IR, 32, int); break; in do_mathemu()
481 case FDTOS: FP_CONV (S, D, 1, 1, SR, DB); break; in do_mathemu()
482 case FQTOS: FP_CONV (S, Q, 1, 2, SR, QB); break; in do_mathemu()
[all …]
/linux/drivers/gpu/drm/amd/display/dc/resource/dcn401/
H A Ddcn401_resource.c99 #define SR(reg_name)\ macro
508 SR(DCHUBBUB_GLOBAL_TIMER_CNTL), \
509 SR(DIO_MEM_PWR_CTRL), \
510 SR(ODM_MEM_PWR_CTRL3), \
511 SR(MMHUBBUB_MEM_PWR_CNTL), \
512 SR(DCCG_GATE_DISABLE_CNTL), \
513 SR(DCCG_GATE_DISABLE_CNTL2), \
514 SR(DCFCLK_CNTL),\
515 SR(DC_MEM_GLOBAL_PWR_REQ_CNTL), \
524 SR(MICROSECOND_TIME_BASE_DIV), \
[all …]

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