| /linux/include/dt-bindings/clock/ |
| H A D | rockchip,rk3506-cru.h | 121 #define SCLK_UART4 108 macro
|
| H A D | rk3308-cru.h | 25 #define SCLK_UART4 21 macro
|
| H A D | px30-cru.h | 29 #define SCLK_UART4 27 macro
|
| H A D | rk3288-cru.h | 36 #define SCLK_UART4 81 macro
|
| H A D | rk3368-cru.h | 34 #define SCLK_UART4 81 macro
|
| H A D | rockchip,rv1126b-cru.h | 41 #define SCLK_UART4 28 macro
|
| H A D | rockchip,rk3528-cru.h | 43 #define SCLK_UART4 31 macro
|
| H A D | rockchip,rv1126-cru.h | 94 #define SCLK_UART4 28 macro
|
| H A D | rockchip,rk3576-cru.h | 161 #define SCLK_UART4 143 macro
|
| H A D | rockchip,rk3588-cru.h | 198 #define SCLK_UART4 183 macro
|
| H A D | rk3568-cru.h | 363 #define SCLK_UART4 299 macro
|
| /linux/drivers/clk/rockchip/ |
| H A D | clk-rk3368.c | 271 MUX(SCLK_UART4, "sclk_uart4", mux_uart4_p, CLK_SET_RATE_PARENT,
|
| H A D | clk-rk3506.c | 430 COMPOSITE(SCLK_UART4, "sclk_uart4", sclk_uart_parents_p, 0,
|
| H A D | clk-rk3288.c | 279 MUX(SCLK_UART4, "sclk_uart4", mux_uart4_p, CLK_SET_RATE_PARENT,
|
| H A D | clk-rk3308.c | 377 GATE(SCLK_UART4, "clk_uart4", "clk_uart4_mux", 0,
|
| H A D | clk-px30.c | 710 GATE(SCLK_UART4, "clk_uart4", "clk_uart4_mux", CLK_SET_RATE_PARENT,
|
| H A D | clk-rv1126.c | 499 GATE(SCLK_UART4, "sclk_uart4", "sclk_uart4_mux", 0,
|
| H A D | clk-rk3528.c | 350 GATE(SCLK_UART4, "sclk_uart4", "clk_uart4", 0,
|
| H A D | clk-rv1126b.c | 279 COMPOSITE(SCLK_UART4, "sclk_uart4", mux_sclk_uart_src_p, 0,
|
| H A D | clk-rk3568.c | 1256 GATE(SCLK_UART4, "sclk_uart4", "sclk_uart4_mux", 0,
|
| H A D | clk-rk3576.c | 675 COMPOSITE(SCLK_UART4, "sclk_uart4", clk_uart_p, 0,
|
| /linux/arch/arm/boot/dts/rockchip/ |
| H A D | rv1126.dtsi | 500 clocks = <&cru SCLK_UART4>, <&cru PCLK_UART4>;
|
| /linux/arch/arm64/boot/dts/rockchip/ |
| H A D | rk3562.dtsi | 815 clocks = <&cru SCLK_UART4>, <&cru PCLK_UART4>;
|
| H A D | rk3528.dtsi | 748 clocks = <&cru SCLK_UART4>, <&cru PCLK_UART4>;
|
| H A D | rk3368.dtsi | 373 clocks = <&cru SCLK_UART4>, <&cru PCLK_UART4>;
|