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/freebsd/contrib/llvm-project/llvm/include/llvm/CodeGen/
H A DMachineRegisterInfo.h61 virtual void MRI_NoteNewVirtualRegister(Register Reg) = 0;
62 virtual void MRI_NoteCloneVirtualRegister(Register NewReg, in MRI_NoteCloneVirtualRegister()
63 Register SrcReg) { in MRI_NoteCloneVirtualRegister()
106 IndexedMap<std::pair<unsigned, SmallVector<Register, 4>>,
116 MachineOperand *&getRegUseDefListHead(Register RegNo) { in getRegUseDefListHead()
122 MachineOperand *getRegUseDefListHead(Register RegNo) const { in getRegUseDefListHead()
152 std::vector<std::pair<MCRegister, Register>> LiveIns;
179 void noteNewVirtualRegister(Register Reg) { in noteNewVirtualRegister()
184 void noteCloneVirtualRegister(Register NewReg, Register SrcReg) { in noteCloneVirtualRegister()
225 bool shouldTrackSubRegLiveness(Register VReg) const { in shouldTrackSubRegLiveness()
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H A DRegister.h19 class Register {
23 constexpr Register(unsigned Val = 0) : Reg(Val) {} in Reg()
24 constexpr Register(MCRegister Val) : Reg(Val.id()) {} in Register() function
44 return Register::FirstStackSlot <= Reg && Reg < Register::VirtualRegFlag; in isStack()
48 static Register index2StackSlot(int FI) { in index2StackSlot()
50 return Register(FI + Register::FirstStackSlot); in index2StackSlot()
62 return Reg & Register::VirtualRegFlag; in isVirtualRegister()
67 static Register index2VirtReg(unsigned Index) { in index2VirtReg()
69 return Index | Register::VirtualRegFlag; in index2VirtReg()
84 return Reg & ~Register::VirtualRegFlag; in virtRegIndex()
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H A DFastISel.h91 Register ResultReg;
96 SmallVector<Register, 16> OutRegs;
98 SmallVector<Register, 4> InRegs;
202 DenseMap<const Value *, Register> LocalValueMap;
269 Register getRegForValue(const Value *V);
274 Register lookUpRegForValue(const Value *V);
278 Register getRegForGEPIndex(MVT PtrVT, const Value *Idx);
351 virtual Register fastEmit_(MVT VT, MVT RetVT, unsigned Opcode);
355 virtual Register fastEmit_r(MVT VT, MVT RetVT, unsigned Opcode, Register Op0);
359 virtual Register fastEmit_rr(MVT VT, MVT RetVT, unsigned Opcode, Register Op0,
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H A DFunctionLoweringInfo.h73 Register DemoteRegister;
81 DenseMap<const Value *, Register> ValueMap;
88 DenseMap<Register, const Value*> VirtReg2Value;
92 const Value *getValueFromVirtualReg(Register Vreg);
95 DenseMap<const Value *, Register> CatchPadExceptionPointers;
118 Register Reg;
146 DenseMap<Register, Register> RegFixups;
148 DenseSet<Register> RegsWithFixups;
182 std::vector<std::pair<MachineInstr*, Register>> PHINodesToUpdate;
188 Register ExceptionPointerVirtReg, ExceptionSelectorVirtReg;
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H A DVirtRegMap.h56 IndexedMap<Register, VirtReg2IndexFunctor> Virt2SplitMap;
60 DenseMap<Register, ShapeT> Virt2ShapeMap;
87 bool hasPhys(Register virtReg) const { return getPhys(virtReg).isValid(); } in hasPhys()
91 MCRegister getPhys(Register virtReg) const { in getPhys()
98 LLVM_ABI void assignVirt2Phys(Register virtReg, MCRegister physReg);
102 bool hasShape(Register virtReg) const { in hasShape()
106 ShapeT getShape(Register virtReg) const { in getShape()
111 void assignVirt2Shape(Register virtReg, ShapeT shape) { in assignVirt2Shape()
117 void clearVirt(Register virtReg) { in clearVirt()
131 LLVM_ABI bool hasPreferredPhys(Register VirtReg) const;
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H A DLiveVariables.h108 LLVM_ABI bool isLiveIn(const MachineBasicBlock &MBB, Register Reg,
139 std::vector<SmallVector<Register, 4>> PHIVarInfo;
153 bool HandlePhysRegKill(Register Reg, MachineInstr *MI);
158 void HandlePhysRegUse(Register Reg, MachineInstr &MI);
159 void HandlePhysRegDef(Register Reg, MachineInstr *MI,
160 SmallVectorImpl<Register> &Defs);
161 void UpdatePhysRegDefs(MachineInstr &MI, SmallVectorImpl<Register> &Defs);
165 MachineInstr *FindLastRefOrPartRef(Register Reg);
170 MachineInstr *FindLastPartialDef(Register Reg,
171 SmallSet<Register, 4> &PartDefRegs);
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H A DLiveRangeEdit.h56 virtual bool LRE_CanEraseVirtReg(Register) { return true; } in LRE_CanEraseVirtReg() argument
59 virtual void LRE_WillShrinkVirtReg(Register) {} in LRE_WillShrinkVirtReg() argument
63 virtual void LRE_DidCloneVirtReg(Register New, Register Old) {} in LRE_DidCloneVirtReg()
68 SmallVectorImpl<Register> &NewRegs;
107 void MRI_NoteNewVirtualRegister(Register VReg) override;
114 LiveInterval &createEmptyIntervalFrom(Register OldReg, bool createSubRanges);
128 LiveRangeEdit(const LiveInterval *parent, SmallVectorImpl<Register> &newRegs,
145 Register getReg() const { return getParent().reg(); } in getReg()
148 using iterator = SmallVectorImpl<Register>::const_iterator;
153 Register get(unsigned idx) const { return NewRegs[idx + FirstNew]; } in get()
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/freebsd/contrib/llvm-project/llvm/include/llvm/CodeGen/GlobalISel/
H A DUtils.h96 LLVM_ABI Register constrainRegToClass(MachineRegisterInfo &MRI,
98 const RegisterBankInfo &RBI, Register Reg,
109 LLVM_ABI Register constrainOperandRegClass(
125 LLVM_ABI Register constrainOperandRegClass(
147 LLVM_ABI bool canReplaceReg(Register DstReg, Register SrcReg,
181 getIConstantVRegVal(Register VReg, const MachineRegisterInfo &MRI);
185 getIConstantVRegSExtVal(Register VReg, const MachineRegisterInfo &MRI);
188 LLVM_ABI const APInt &getIConstantFromReg(Register VReg,
195 Register VReg;
201 getIConstantVRegValWithLookThrough(Register VReg,
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H A DCombinerHelper.h57 Register Addr;
58 Register Base;
59 Register Offset;
67 Register Base;
72 Register Reg;
79 Register LogicNonShiftReg;
155 void replaceRegWith(MachineRegisterInfo &MRI, Register FromReg, Register ToReg) const;
160 Register ToReg) const;
171 const RegisterBank *getRegBank(Register Reg) const;
176 void setRegBank(Register Reg, const RegisterBank *RegBank) const;
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H A DGISelValueTracking.h41 SmallDenseMap<Register, KnownBits, 16> ComputeKnownBitsCache;
43 void computeKnownBitsMin(Register Src0, Register Src1, KnownBits &Known,
46 unsigned computeNumSignBitsMin(Register Src0, Register Src1,
49 void computeKnownFPClass(Register R, KnownFPClass &Known,
57 void computeKnownFPClass(Register R, const APInt &DemandedElts,
69 virtual void computeKnownBitsImpl(Register R, KnownBits &Known,
73 unsigned computeNumSignBits(Register R, const APInt &DemandedElts,
75 unsigned computeNumSignBits(Register R, unsigned Depth = 0);
78 KnownBits getKnownBits(Register R);
79 KnownBits getKnownBits(Register R, const APInt &DemandedElts,
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H A DCallLowering.h64 SmallVector<Register, 4> Regs;
68 SmallVector<Register, 2> OrigRegs;
82 ArgInfo(ArrayRef<Register> Regs, Type *Ty, unsigned OrigIndex,
95 ArgInfo(ArrayRef<Register> Regs, const Value &OrigValue, unsigned OrigIndex,
105 Register Discriminator;
124 Register SwiftErrorVReg;
127 Register ConvergenceCtrlToken;
155 Register DemoteRegister;
266 virtual Register getStackAddress(uint64_t MemSize, int64_t Offset,
282 virtual void assignValueToReg(Register ValVReg, Register PhysReg,
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H A DLegalizationArtifactCombiner.h61 SmallVectorImpl<Register> &UpdatedDefs, in tryCombineAnyExt()
67 Register DstReg = MI.getOperand(0).getReg(); in tryCombineAnyExt()
68 Register SrcReg = lookThroughCopyInstrs(MI.getOperand(1).getReg()); in tryCombineAnyExt()
71 Register TruncSrc; in tryCombineAnyExt()
85 Register ExtSrc; in tryCombineAnyExt()
120 SmallVectorImpl<Register> &UpdatedDefs, in tryCombineZExt()
126 Register DstReg = MI.getOperand(0).getReg(); in tryCombineZExt()
127 Register SrcReg = lookThroughCopyInstrs(MI.getOperand(1).getReg()); in tryCombineZExt()
131 Register TruncSrc; in tryCombineZExt()
132 Register SextSrc; in tryCombineZExt()
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/freebsd/contrib/llvm-project/llvm/lib/CodeGen/
H A DMachineSSAUpdater.cpp37 using AvailableValsTy = DenseMap<MachineBasicBlock *, Register>;
54 void MachineSSAUpdater::Initialize(Register V) { in Initialize()
71 void MachineSSAUpdater::AddAvailableValue(MachineBasicBlock *BB, Register V) { in AddAvailableValue()
77 Register MachineSSAUpdater::GetValueAtEndOfBlock(MachineBasicBlock *BB) { in GetValueAtEndOfBlock()
82 Register LookForIdenticalPHI(MachineBasicBlock *BB, in LookForIdenticalPHI()
83 SmallVectorImpl<std::pair<MachineBasicBlock *, Register>> &PredValues) { in LookForIdenticalPHI()
85 return Register(); in LookForIdenticalPHI()
89 return Register(); in LookForIdenticalPHI()
97 Register SrcReg = I->getOperand(i).getReg(); in LookForIdenticalPHI()
108 return Register(); in LookForIdenticalPHI()
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H A DRegAllocGreedy.h86 LiveRangeStage getStage(Register Reg) const { return Info[Reg].Stage; } in getStage()
92 void setStage(Register Reg, LiveRangeStage Stage) { in setStage()
103 LiveRangeStage getOrInitStage(Register Reg) { in getOrInitStage()
108 unsigned getCascade(Register Reg) const { return Info[Reg].Cascade; } in getCascade()
110 void setCascade(Register Reg, unsigned Cascade) { in setCascade()
115 unsigned getOrAssignNewCascade(Register Reg) { in getOrAssignNewCascade()
124 unsigned getCascadeOrCurrentNext(Register Reg) const { in getCascadeOrCurrentNext()
134 Register Reg = *Begin; in setStage()
140 void LRE_DidCloneVirtReg(Register New, Register Old);
296 SmallVectorImpl<Register> &) override;
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H A DMachineRegisterInfo.cpp58 MachineRegisterInfo::setRegClass(Register Reg, const TargetRegisterClass *RC) { in setRegClass()
63 void MachineRegisterInfo::setRegBank(Register Reg, in setRegBank()
69 constrainRegClass(MachineRegisterInfo &MRI, Register Reg, in constrainRegClass()
85 Register Reg, const TargetRegisterClass *RC, unsigned MinNumRegs) { in constrainRegClass()
92 MachineRegisterInfo::constrainRegAttrs(Register Reg, in constrainRegAttrs()
93 Register ConstrainingReg, in constrainRegAttrs()
122 MachineRegisterInfo::recomputeRegClass(Register Reg) { in recomputeRegClass()
145 Register MachineRegisterInfo::createIncompleteVirtualRegister(StringRef Name) { in createIncompleteVirtualRegister()
146 Register Reg = Register::index2VirtReg(getNumVirtRegs()); in createIncompleteVirtualRegister()
155 Register
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H A DTwoAddressInstructionPass.cpp115 DenseMap<Register, Register> SrcRegMap;
120 DenseMap<Register, Register> DstRegMap;
122 MachineInstr *getSingleDef(Register Reg, MachineBasicBlock *BB) const;
124 bool isRevCopyChain(Register FromReg, Register ToReg, int Maxlen);
126 bool noUseAfterLastDef(Register Reg, unsigned Dist, unsigned &LastDef);
128 bool isCopyToReg(MachineInstr &MI, Register &SrcReg, Register &DstReg,
132 bool isPlainlyKilled(const MachineInstr *MI, Register Reg) const;
135 bool isKilled(MachineInstr &MI, Register Reg, bool allowFalsePositives) const;
137 MachineInstr *findOnlyInterestingUse(Register Reg, MachineBasicBlock *MBB,
138 bool &IsCopy, Register &DstReg,
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/freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DAMDGPUGlobalISelDivergenceLowering.cpp63 Register buildRegCopyToLaneMask(Register Reg);
66 void markAsLaneMask(Register DstReg) const override;
72 void replaceDstReg(Register NewReg, Register OldReg,
76 Register DstReg, Register PrevReg,
77 Register CurReg) override;
90 void DivergenceLoweringHelper::markAsLaneMask(Register DstReg) const { in markAsLaneMask()
109 Register Dst = MI.getOperand(0).getReg(); in getCandidatesForLowering()
120 MI->getOperand(i + 1).getMBB(), Register()); in collectIncomingValuesFromPhi()
124 void DivergenceLoweringHelper::replaceDstReg(Register NewReg, Register OldReg, in replaceDstReg()
132 Register DivergenceLoweringHelper::buildRegCopyToLaneMask(Register Reg) { in buildRegCopyToLaneMask()
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H A DSILowerI1Copies.h27 Register Reg;
29 Register UpdatedReg;
31 Incoming(Register Reg, MachineBasicBlock *Block, Register UpdatedReg) in Incoming()
35 Register createLaneMaskReg(MachineRegisterInfo *MRI,
55 DenseSet<Register> PhiRegisters;
58 Register ExecReg;
68 bool isConstantLaneMask(Register Reg, bool &Val) const;
72 void initializeLaneMaskRegisterAttributes(Register LaneMask) { in initializeLaneMaskRegisterAttributes()
81 bool isLaneMaskReg(Register Reg) const { in isLaneMaskReg()
89 virtual void markAsLaneMask(Register DstReg) const = 0;
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H A DSIMachineFunctionInfo.h381 Register Reg;
386 PrologEpilogSGPRSaveRestoreInfo(SGPRSaveKind K, Register R)
388 Register getReg() const { return Reg; }
394 using argument_type = Register;
395 unsigned operator()(Register Reg) const {
414 Register ScratchRSrcReg = AMDGPU::PRIVATE_RSRC_REG;
418 Register FrameOffsetReg = AMDGPU::FP_REG;
423 Register StackPtrOffsetReg = AMDGPU::SP_REG;
428 Register LongBranchReservedReg;
524 void MRI_NoteNewVirtualRegister(Register Reg) override;
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H A DAMDGPULegalizerInfo.h40 Register getSegmentAperture(unsigned AddrSpace,
67 bool buildPCRelGlobalAddress(Register DstReg, LLT PtrTy, MachineIRBuilder &B,
71 void buildAbsGlobalAddress(Register DstReg, LLT PtrTy, MachineIRBuilder &B,
86 std::pair<Register, Register>
87 getScaledLogInput(MachineIRBuilder &B, Register Src, unsigned Flags) const;
91 bool legalizeFlogUnsafe(MachineIRBuilder &B, Register Dst, Register Src,
94 bool legalizeFExpUnsafe(MachineIRBuilder &B, Register Dst, Register Src,
104 void buildMultiply(LegalizerHelper &Helper, MutableArrayRef<Register> Accum,
105 ArrayRef<Register> Src0, ArrayRef<Register> Src1,
114 void buildLoadInputValue(Register DstReg, MachineIRBuilder &B,
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H A DAMDGPURegisterBankInfo.h18 #include "llvm/CodeGen/Register.h"
48 bool buildVCopy(MachineIRBuilder &B, Register DstReg, Register SrcReg) const;
51 SmallSet<Register, 4> &SGPROperandRegs,
58 SmallSet<Register, 4> &SGPROperandRegs) const;
60 Register buildReadFirstLane(MachineIRBuilder &B, MachineRegisterInfo &MRI,
61 Register Src) const;
75 unsigned setBufferOffsets(MachineIRBuilder &B, Register CombinedOffset,
76 Register &VOffsetReg, Register
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/freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64FastISel.cpp96 Register OffsetReg;
111 void setReg(Register Reg) { in setReg()
116 Register getReg() const { in getReg()
121 void setOffsetReg(Register Reg) { OffsetReg = Reg; } in setOffsetReg()
123 Register getOffsetReg() const { return OffsetReg; } in getOffsetReg()
196 Register getRegForGEPIndex(const Value *Idx);
199 Register emitAddSub(bool UseAdd, MVT RetVT, const Value *LHS,
202 Register emitAddSub_rr(bool UseAdd, MVT RetVT, Register LHSReg,
203 Register RHSReg, bool SetFlags = false,
205 Register emitAddSub_ri(bool UseAdd, MVT RetVT, Register LHSReg, uint64_t Imm,
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/freebsd/contrib/llvm-project/llvm/lib/Target/SystemZ/
H A DSystemZMachineFunctionInfo.h35 Register VarArgsFirstGPR;
36 Register VarArgsFirstFPR;
42 Register VRegADA;
64 void setSpillGPRRegs(Register Low, Register High, unsigned Offs) { in setSpillGPRRegs()
74 void setRestoreGPRRegs(Register Low, Register High, unsigned Offs) { in setRestoreGPRRegs()
82 Register getVarArgsFirstGPR() const { return VarArgsFirstGPR; } in getVarArgsFirstGPR()
83 void setVarArgsFirstGPR(Register GPR) { VarArgsFirstGPR = GPR; } in setVarArgsFirstGPR()
86 Register getVarArgsFirstFP
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/freebsd/contrib/llvm-project/llvm/lib/Target/VE/
H A DVERegisterInfo.cpp65 const Register ReservedRegs[] = { in getReservedRegs()
132 Register clobber;
142 inline MachineInstrBuilder build(const MCInstrDesc &MCID, Register DestReg) { in build()
145 inline MachineInstrBuilder build(unsigned InstOpc, Register DestReg) { in build()
158 void prepareReplaceFI(MachineInstr &MI, Register &FrameReg, int64_t &Offset,
163 void replaceFI(MachineInstr &MI, Register FrameReg, int64_t Offset,
167 void processSTQ(MachineInstr &MI, Register FrameReg, int64_t Offset,
169 void processLDQ(MachineInstr &MI, Register FrameReg, int64_t Offset,
172 void processSTVM(MachineInstr &MI, Register FrameReg, int64_t Offset,
174 void processLDVM(MachineInstr &MI, Register FrameReg, int64_t Offset,
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/freebsd/contrib/llvm-project/llvm/lib/Target/PowerPC/GISel/
H A DPPCCallLowering.cpp35 void assignValueToReg(Register ValVReg, Register PhysReg,
37 void assignValueToAddress(Register ValVReg, Register Addr, LLT MemTy,
40 Register getStackAddress(uint64_t Size, int64_t Offset,
48 void OutgoingArgHandler::assignValueToReg(Register ValVReg, Register PhysReg, in assignValueToReg()
51 Register ExtReg = extendRegister(ValVReg, VA); in assignValueToReg()
55 void OutgoingArgHandler::assignValueToAddress(Register ValVReg, Register Addr, in assignValueToAddress()
62 Register OutgoingArgHandler::getStackAddress(uint64_t Size, int64_t Offset, in getStackAddress()
72 const Value *Val, ArrayRef<Register> VRegs, in lowerReturn()
74 Register SwiftErrorVReg) const { in lowerReturn()
113 ArrayRef<ArrayRef<Register>> VRegs, in lowerFormalArguments()
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