1d2912cb1SThomas Gleixner/* SPDX-License-Identifier: GPL-2.0-only */ 25f58c970SAlexandre Belloni/* 35f58c970SAlexandre Belloni * Copyright (C) 2003-2005 SAN People 45f58c970SAlexandre Belloni * 55f58c970SAlexandre Belloni * Debugging macro include header 65f58c970SAlexandre Belloni*/ 75f58c970SAlexandre Belloni 85f58c970SAlexandre Belloni#define AT91_DBGU_SR (0x14) /* Status Register */ 95f58c970SAlexandre Belloni#define AT91_DBGU_THR (0x1c) /* Transmitter Holding Register */ 105f58c970SAlexandre Belloni#define AT91_DBGU_TXRDY (1 << 1) /* Transmitter Ready */ 115f58c970SAlexandre Belloni#define AT91_DBGU_TXEMPTY (1 << 9) /* Transmitter Empty */ 125f58c970SAlexandre Belloni 135f58c970SAlexandre Belloni .macro addruart, rp, rv, tmp 146f112a08SAlexandre Belloni ldr \rp, =CONFIG_DEBUG_UART_PHYS @ System peripherals (phys address) 150b37e9e8SAlexandre Belloni ldr \rv, =CONFIG_DEBUG_UART_VIRT @ System peripherals (virt address) 165f58c970SAlexandre Belloni .endm 175f58c970SAlexandre Belloni 185f58c970SAlexandre Belloni .macro senduart,rd,rx 195f58c970SAlexandre Belloni strb \rd, [\rx, #(AT91_DBGU_THR)] @ Write to Transmitter Holding Register 205f58c970SAlexandre Belloni .endm 215f58c970SAlexandre Belloni 22*2c50a570SLinus Walleij .macro waituarttxrdy,rd,rx 235f58c970SAlexandre Belloni1001: ldr \rd, [\rx, #(AT91_DBGU_SR)] @ Read Status Register 245f58c970SAlexandre Belloni tst \rd, #AT91_DBGU_TXRDY @ DBGU_TXRDY = 1 when ready to transmit 255f58c970SAlexandre Belloni beq 1001b 265f58c970SAlexandre Belloni .endm 275f58c970SAlexandre Belloni 28*2c50a570SLinus Walleij .macro waituartcts,rd,rx 29*2c50a570SLinus Walleij .endm 30*2c50a570SLinus Walleij 315f58c970SAlexandre Belloni .macro busyuart,rd,rx 325f58c970SAlexandre Belloni1001: ldr \rd, [\rx, #(AT91_DBGU_SR)] @ Read Status Register 335f58c970SAlexandre Belloni tst \rd, #AT91_DBGU_TXEMPTY @ DBGU_TXEMPTY = 1 when transmission complete 345f58c970SAlexandre Belloni beq 1001b 355f58c970SAlexandre Belloni .endm 365f58c970SAlexandre Belloni 37