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Searched refs:RREG32_SOC15 (Results 1 – 25 of 94) sorted by relevance

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/linux/drivers/gpu/drm/amd/amdgpu/
H A Dnbio_v4_3.c42 u32 tmp = RREG32_SOC15(NBIO, 0, regRCC_STRAP0_RCC_DEV0_EPF0_STRAP0); in nbio_v4_3_get_rev_id()
62 return RREG32_SOC15(NBIO, 0, regRCC_DEV0_EPF0_RCC_CONFIG_MEMSIZE); in nbio_v4_3_get_memsize()
70 u32 doorbell_range = RREG32_SOC15(NBIO, 0, regS2A_DOORBELL_ENTRY_2_CTRL); in nbio_v4_3_sdma_doorbell_range()
109 doorbell_range = RREG32_SOC15(NBIO, 0, regS2A_DOORBELL_ENTRY_5_CTRL); in nbio_v4_3_vcn_doorbell_range()
111 doorbell_range = RREG32_SOC15(NBIO, 0, regS2A_DOORBELL_ENTRY_4_CTRL); in nbio_v4_3_vcn_doorbell_range()
185 u32 ih_doorbell_range = RREG32_SOC15(NBIO, 0, regS2A_DOORBELL_ENTRY_1_CTRL); in nbio_v4_3_ih_doorbell_range()
224 interrupt_cntl = RREG32_SOC15(NBIO, 0, regBIF_BX0_INTERRUPT_CNTL); in nbio_v4_3_ih_control()
247 def = data = RREG32_SOC15(NBIO, 0, regCPM_CONTROL); in nbio_v4_3_update_medium_grain_clock_gating()
277 def = data = RREG32_SOC15(NBIO, 0, regPCIE_CNTL2); in nbio_v4_3_update_medium_grain_light_sleep()
294 data = RREG32_SOC15(NBIO, 0, regCPM_CONTROL); in nbio_v4_3_get_clockgating_state()
[all …]
H A Dnbif_v6_3_1.c43 u32 tmp = RREG32_SOC15(NBIO, 0, regRCC_STRAP0_RCC_DEV0_EPF0_STRAP0); in nbif_v6_3_1_get_rev_id()
63 return RREG32_SOC15(NBIO, 0, regRCC_DEV0_EPF0_RCC_CONFIG_MEMSIZE); in nbif_v6_3_1_get_memsize()
72 u32 doorbell_range = RREG32_SOC15(NBIO, 0, regGDC_S2A0_S2A_DOORBELL_ENTRY_2_CTRL); in nbif_v6_3_1_sdma_doorbell_range()
112 doorbell_range = RREG32_SOC15(NBIO, 0, regGDC_S2A0_S2A_DOORBELL_ENTRY_5_CTRL); in nbif_v6_3_1_vcn_doorbell_range()
114 doorbell_range = RREG32_SOC15(NBIO, 0, regGDC_S2A0_S2A_DOORBELL_ENTRY_4_CTRL); in nbif_v6_3_1_vcn_doorbell_range()
188 u32 ih_doorbell_range = RREG32_SOC15(NBIO, 0, regGDC_S2A0_S2A_DOORBELL_ENTRY_1_CTRL); in nbif_v6_3_1_ih_doorbell_range()
227 interrupt_cntl = RREG32_SOC15(NBIO, 0, regBIF_BX0_INTERRUPT_CNTL); in nbif_v6_3_1_ih_control()
299 data = RREG32_SOC15(NBIO, 0, regRCC_DEV0_EPF2_STRAP2); in nbif_v6_3_1_init_registers()
308 data = RREG32_SOC15(NBIO, 0, regREGS_ROM_OFFSET_CTRL); in nbif_v6_3_1_get_rom_offset()
320 def = RREG32_SOC15(NBIO, 0, regRCC_EP_DEV0_0_EP_PCIE_TX_LTR_CNTL); in nbif_v6_3_1_program_ltr()
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H A Dimu_v12_0.c124 imu_reg_val = RREG32_SOC15(GC, 0, regGFX_IMU_GFX_RESET_CTRL); in imu_v12_0_wait_for_reset_status()
146 imu_reg_val = RREG32_SOC15(GC, 0, regGFX_IMU_C2PMSG_16); in imu_v12_0_setup()
150 imu_reg_val = RREG32_SOC15(GC, 0, regGFX_IMU_SCRATCH_10); in imu_v12_0_setup()
161 imu_reg_val = RREG32_SOC15(GC, 0, regGFX_IMU_CORE_CTRL); in imu_v12_0_start()
303 return RREG32_SOC15(MMHUB, 0, regMMMC_VM_FB_LOCATION_BASE); in imu_v12_init_gfxhub_settings()
305 return RREG32_SOC15(MMHUB, 0, regMMMC_VM_FB_LOCATION_TOP); in imu_v12_init_gfxhub_settings()
307 return RREG32_SOC15(MMHUB, 0, regMMMC_VM_FB_OFFSET); in imu_v12_init_gfxhub_settings()
309 return RREG32_SOC15(MMHUB, 0, regMMMC_VM_AGP_BASE); in imu_v12_init_gfxhub_settings()
311 return RREG32_SOC15(MMHUB, 0, regMMMC_VM_AGP_BOT); in imu_v12_init_gfxhub_settings()
313 return RREG32_SOC15(MMHUB, 0, regMMMC_VM_AGP_TOP); in imu_v12_init_gfxhub_settings()
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H A Dgfxhub_v2_1.c110 u64 base = RREG32_SOC15(GC, 0, mmGCMC_VM_FB_LOCATION_BASE); in gfxhub_v2_1_get_fb_location()
120 return (u64)RREG32_SOC15(GC, 0, mmGCMC_VM_FB_OFFSET) << 24; in gfxhub_v2_1_get_mc_fb_offset()
195 tmp = RREG32_SOC15(GC, 0, mmGCMC_VM_MX_L1_TLB_CNTL); in gfxhub_v2_1_init_tlb_regs()
220 tmp = RREG32_SOC15(GC, 0, mmGCVM_L2_CNTL); in gfxhub_v2_1_init_cache_regs()
233 tmp = RREG32_SOC15(GC, 0, mmGCVM_L2_CNTL2); in gfxhub_v2_1_init_cache_regs()
264 tmp = RREG32_SOC15(GC, 0, mmGCVM_CONTEXT0_CNTL); in gfxhub_v2_1_enable_system_domain()
397 tmp = RREG32_SOC15(GC, 0, mmGCMC_VM_MX_L1_TLB_CNTL); in gfxhub_v2_1_gart_disable()
428 tmp = RREG32_SOC15(GC, 0, mmGCVM_L2_PROTECTION_FAULT_CNTL); in gfxhub_v2_1_set_fault_enable_default()
510 u32 xgmi_lfb_cntl = RREG32_SOC15(GC, 0, mmGCMC_VM_XGMI_LFB_CNTL); in gfxhub_v2_1_get_xgmi_info()
537 RREG32_SOC15(GC, 0, mmGCMC_VM_XGMI_LFB_SIZE), in gfxhub_v2_1_get_xgmi_info()
[all …]
H A Dnbio_v7_7.c43 tmp = RREG32_SOC15(NBIO, 0, regRCC_STRAP0_RCC_DEV0_EPF0_STRAP0); in nbio_v7_7_get_rev_id()
62 return RREG32_SOC15(NBIO, 0, regRCC_DEV0_EPF0_0_RCC_CONFIG_MEMSIZE); in nbio_v7_7_get_memsize()
113 reg = RREG32_SOC15(NBIO, 0, regRCC_DEV0_EPF0_0_RCC_DOORBELL_APER_EN); in nbio_v7_7_enable_doorbell_aperture()
149 u32 ih_doorbell_range = RREG32_SOC15(NBIO, 0, in nbio_v7_7_ih_doorbell_range()
177 interrupt_cntl = RREG32_SOC15(NBIO, 0, regBIF_BX1_INTERRUPT_CNTL); in nbio_v7_7_ih_control()
241 def = data = RREG32_SOC15(NBIO, 0, regBIF0_PCIE_MST_CTRL_3); in nbio_v7_7_init_registers()
252 data = RREG32_SOC15(NBIO, 0, regRCC_DEV0_EPF5_STRAP4) & ~BIT(23); in nbio_v7_7_init_registers()
266 def = data = RREG32_SOC15(NBIO, 0, regBIF0_CPM_CONTROL); in nbio_v7_7_update_medium_grain_clock_gating()
295 def = data = RREG32_SOC15(NBIO, 0, regBIF0_PCIE_CNTL2); in nbio_v7_7_update_medium_grain_light_sleep()
304 def = data = RREG32_SOC15(NBIO, 0, regBIF0_PCIE_TX_POWER_CTRL_1); in nbio_v7_7_update_medium_grain_light_sleep()
[all …]
H A Dnbio_v7_11.c43 tmp = RREG32_SOC15(NBIO, 0, regRCC_STRAP1_RCC_DEV0_EPF0_STRAP0); in nbio_v7_11_get_rev_id()
62 return RREG32_SOC15(NBIO, 0, regRCC_DEV0_EPF0_0_RCC_CONFIG_MEMSIZE); in nbio_v7_11_get_memsize()
143 reg = RREG32_SOC15(NBIO, 0, regRCC_DEV0_EPF0_0_RCC_DOORBELL_APER_EN); in nbio_v7_11_enable_doorbell_aperture()
178 u32 ih_doorbell_range = RREG32_SOC15(NBIO, 0,regGDC0_BIF_IH_DOORBELL_RANGE); in nbio_v7_11_ih_doorbell_range()
205 interrupt_cntl = RREG32_SOC15(NBIO, 0, regBIF_BX1_INTERRUPT_CNTL); in nbio_v7_11_ih_control()
269 def = data = RREG32_SOC15(NBIO, 0, regBIF_BIF256_CI256_RC3X4_USB4_PCIE_MST_CTRL_3); in nbio_v7_11_init_registers()
283 data = RREG32_SOC15(NBIO, 0, regRCC_DEV0_EPF5_STRAP4) & ~BIT(23); in nbio_v7_11_init_registers()
297 def = data = RREG32_SOC15(NBIO, 0, regBIF_BIF256_CI256_RC3X4_USB4_CPM_CONTROL); in nbio_v7_11_update_medium_grain_clock_gating()
326 def = data = RREG32_SOC15(NBIO, 0, regBIF_BIF256_CI256_RC3X4_USB4_PCIE_CNTL2); in nbio_v7_11_update_medium_grain_light_sleep()
335 def = data = RREG32_SOC15(NBIO, 0, regBIF_BIF256_CI256_RC3X4_USB4_PCIE_TX_POWER_CTRL_1); in nbio_v7_11_update_medium_grain_light_sleep()
[all …]
H A Dsmuio_v13_0.c48 def = data = RREG32_SOC15(SMUIO, 0, regCGTT_ROM_CLK_CTRL0); in smuio_v13_0_update_rom_clock_gating()
69 data = RREG32_SOC15(SMUIO, 0, regCGTT_ROM_CLK_CTRL0); in smuio_v13_0_get_clock_gating_state()
85 data = RREG32_SOC15(SMUIO, 0, regSMUIO_MCM_CONFIG); in smuio_v13_0_get_die_id()
102 data = RREG32_SOC15(SMUIO, 0, regSMUIO_MCM_CONFIG); in smuio_v13_0_get_socket_id()
119 data = RREG32_SOC15(SMUIO, 0, regSMUIO_MCM_CONFIG); in smuio_v13_0_is_host_gpu_xgmi_supported()
136 data = RREG32_SOC15(SMUIO, 0, regSMUIO_MCM_CONFIG); in smuio_v13_0_get_pkg_type()
H A Dumsch_mm_v4_0.c72 data = RREG32_SOC15(VCN, 0, regUMSCH_MES_RESET_CTRL); in umsch_mm_v4_0_load_microcode()
76 data = RREG32_SOC15(VCN, 0, regVCN_MES_CNTL); in umsch_mm_v4_0_load_microcode()
83 data = RREG32_SOC15(VCN, 0, regVCN_MES_IC_BASE_CNTL); in umsch_mm_v4_0_load_microcode()
129 data = RREG32_SOC15(VCN, 0, regUVD_UMSCH_FORCE); in umsch_mm_v4_0_load_microcode()
134 data = RREG32_SOC15(VCN, 0, regVCN_MES_IC_OP_CNTL); in umsch_mm_v4_0_load_microcode()
139 data = RREG32_SOC15(VCN, 0, regVCN_MES_IC_OP_CNTL); in umsch_mm_v4_0_load_microcode()
154 data = RREG32_SOC15(VCN, 0, regVCN_MES_CNTL); in umsch_mm_v4_0_load_microcode()
167 RREG32_SOC15(VCN, 0, regVCN_MES_MSTATUS_LO)); in umsch_mm_v4_0_load_microcode()
189 data = RREG32_SOC15(VCN, 0, regVCN_AGDB_CTRL0); in umsch_mm_v4_0_aggregated_doorbell_init()
195 data = RREG32_SOC15(VCN, 0, regVCN_AGDB_CTRL1); in umsch_mm_v4_0_aggregated_doorbell_init()
[all …]
H A Dmmhub_v2_3.c179 tmp = RREG32_SOC15(MMHUB, 0, mmMMVM_L2_PROTECTION_FAULT_CNTL2); in mmhub_v2_3_init_system_aperture_regs()
190 tmp = RREG32_SOC15(MMHUB, 0, mmMMMC_VM_MX_L1_TLB_CNTL); in mmhub_v2_3_init_tlb_regs()
209 tmp = RREG32_SOC15(MMHUB, 0, mmMMVM_L2_CNTL); in mmhub_v2_3_init_cache_regs()
222 tmp = RREG32_SOC15(MMHUB, 0, mmMMVM_L2_CNTL2); in mmhub_v2_3_init_cache_regs()
253 tmp = RREG32_SOC15(MMHUB, 0, mmMMVM_CONTEXT0_CNTL); in mmhub_v2_3_enable_system_domain()
386 tmp = RREG32_SOC15(MMHUB, 0, mmMMMC_VM_MX_L1_TLB_CNTL); in mmhub_v2_3_gart_disable()
393 tmp = RREG32_SOC15(MMHUB, 0, mmMMVM_L2_CNTL); in mmhub_v2_3_gart_disable()
410 tmp = RREG32_SOC15(MMHUB, 0, mmMMVM_L2_PROTECTION_FAULT_CNTL); in mmhub_v2_3_set_fault_enable_default()
497 def = data = RREG32_SOC15(MMHUB, 0, mmMM_ATC_L2_CGTT_CLK_CTRL); in mmhub_v2_3_update_medium_grain_clock_gating()
498 def1 = data1 = RREG32_SOC15(MMHUB, 0, mmDAGB0_CNTL_MISC2); in mmhub_v2_3_update_medium_grain_clock_gating()
[all …]
H A Dsmu_v11_0_i2c.c51 uint32_t reg = RREG32_SOC15(SMUIO, 0, mmSMUIO_PWRMGT); in smu_v11_0_i2c_set_clock_gating()
87 u32 en_stat = RREG32_SOC15(SMUIO, in smu_v11_0_i2c_enable()
108 RREG32_SOC15(SMUIO, 0, mmCKSVII2C_IC_CLR_INTR); in smu_v11_0_i2c_clear_status()
187 reg = RREG32_SOC15(SMUIO, 0, mmCKSVII2C_IC_STATUS); in smu_v11_0_i2c_poll_tx_status()
195 reg = RREG32_SOC15(SMUIO, 0, mmCKSVII2C_IC_INTR_STAT); in smu_v11_0_i2c_poll_tx_status()
198 reg_c_tx_abrt_source = RREG32_SOC15(SMUIO, 0, mmCKSVII2C_IC_TX_ABRT_SOURCE); in smu_v11_0_i2c_poll_tx_status()
230 reg_c_tx_abrt_source = RREG32_SOC15(SMUIO, 0, mmCKSVII2C_IC_TX_ABRT_SOURCE); in smu_v11_0_i2c_poll_rx_status()
249 reg_ic_status = RREG32_SOC15(SMUIO, 0, mmCKSVII2C_IC_STATUS); in smu_v11_0_i2c_poll_rx_status()
298 reg = RREG32_SOC15(SMUIO, 0, mmCKSVII2C_IC_STATUS); in smu_v11_0_i2c_transmit()
422 reg = RREG32_SOC15(SMUIO, 0, mmCKSVII2C_IC_DATA_CMD); in smu_v11_0_i2c_receive()
[all …]
H A Dsmuio_v14_0_2.c45 clock_counter_hi_pre = (u64)RREG32_SOC15(SMUIO, 0, regGOLDEN_TSC_COUNT_UPPER); in smuio_v14_0_2_get_gpu_clock_counter()
46 clock_counter_lo = (u64)RREG32_SOC15(SMUIO, 0, regGOLDEN_TSC_COUNT_LOWER); in smuio_v14_0_2_get_gpu_clock_counter()
48 clock_counter_hi_after = (u64)RREG32_SOC15(SMUIO, 0, regGOLDEN_TSC_COUNT_UPPER); in smuio_v14_0_2_get_gpu_clock_counter()
50 clock_counter_lo = (u64)RREG32_SOC15(SMUIO, 0, regGOLDEN_TSC_COUNT_LOWER); in smuio_v14_0_2_get_gpu_clock_counter()
H A Dvcn_v4_0_5.c311 RREG32_SOC15(VCN, i, regUVD_STATUS))) { in vcn_v4_0_5_hw_fini()
585 data = RREG32_SOC15(VCN, inst, regUVD_POWER_STATUS); in vcn_v4_0_5_disable_static_power_gating()
607 data = RREG32_SOC15(VCN, inst, regUVD_POWER_STATUS); in vcn_v4_0_5_enable_static_power_gating()
651 data = RREG32_SOC15(VCN, inst, regUVD_CGC_CTRL); in vcn_v4_0_5_disable_clock_gating()
657 data = RREG32_SOC15(VCN, inst, regUVD_CGC_GATE); in vcn_v4_0_5_disable_clock_gating()
682 data = RREG32_SOC15(VCN, inst, regUVD_CGC_CTRL); in vcn_v4_0_5_disable_clock_gating()
705 data = RREG32_SOC15(VCN, inst, regUVD_SUVD_CGC_GATE); in vcn_v4_0_5_disable_clock_gating()
732 data = RREG32_SOC15(VCN, inst, regUVD_SUVD_CGC_CTRL); in vcn_v4_0_5_disable_clock_gating()
819 data = RREG32_SOC15(VCN, inst, regUVD_CGC_CTRL); in vcn_v4_0_5_enable_clock_gating()
825 data = RREG32_SOC15(VCN, inst, regUVD_CGC_CTRL); in vcn_v4_0_5_enable_clock_gating()
[all …]
H A Ddf_v1_7.c49 tmp = RREG32_SOC15(DF, 0, mmFabricConfigAccessControl); in df_v1_7_enable_broadcast_mode()
61 tmp = RREG32_SOC15(DF, 0, mmDF_CS_AON0_DramBaseAddress0); in df_v1_7_get_fb_channel_number()
88 tmp = RREG32_SOC15(DF, 0, mmDF_PIE_AON0_DfGlobalClkGater); in df_v1_7_update_medium_grain_clock_gating()
93 tmp = RREG32_SOC15(DF, 0, mmDF_PIE_AON0_DfGlobalClkGater); in df_v1_7_update_medium_grain_clock_gating()
109 tmp = RREG32_SOC15(DF, 0, mmDF_PIE_AON0_DfGlobalClkGater); in df_v1_7_get_clockgating_state()
H A Dmmhub_v3_0.c204 tmp = RREG32_SOC15(MMHUB, 0, regMMVM_L2_PROTECTION_FAULT_CNTL2); in mmhub_v3_0_init_system_aperture_regs()
215 tmp = RREG32_SOC15(MMHUB, 0, regMMMC_VM_MX_L1_TLB_CNTL); in mmhub_v3_0_init_tlb_regs()
241 tmp = RREG32_SOC15(MMHUB, 0, regMMVM_L2_CNTL); in mmhub_v3_0_init_cache_regs()
254 tmp = RREG32_SOC15(MMHUB, 0, regMMVM_L2_CNTL2); in mmhub_v3_0_init_cache_regs()
285 tmp = RREG32_SOC15(MMHUB, 0, regMMVM_CONTEXT0_CNTL); in mmhub_v3_0_enable_system_domain()
410 tmp = RREG32_SOC15(MMHUB, 0, regMMMC_VM_MX_L1_TLB_CNTL); in mmhub_v3_0_gart_disable()
417 tmp = RREG32_SOC15(MMHUB, 0, regMMVM_L2_CNTL); in mmhub_v3_0_gart_disable()
439 tmp = RREG32_SOC15(MMHUB, 0, regMMVM_L2_PROTECTION_FAULT_CNTL); in mmhub_v3_0_set_fault_enable_default()
529 base = RREG32_SOC15(MMHUB, 0, regMMMC_VM_FB_LOCATION_BASE); in mmhub_v3_0_get_fb_location()
539 return (u64)RREG32_SOC15(MMHUB, 0, regMMMC_VM_FB_OFFSET) << 24; in mmhub_v3_0_get_mc_fb_offset()
[all …]
H A Dmmhub_v2_0.c249 tmp = RREG32_SOC15(MMHUB, 0, mmMMVM_L2_PROTECTION_FAULT_CNTL2); in mmhub_v2_0_init_system_aperture_regs()
260 tmp = RREG32_SOC15(MMHUB, 0, mmMMMC_VM_MX_L1_TLB_CNTL); in mmhub_v2_0_init_tlb_regs()
285 tmp = RREG32_SOC15(MMHUB, 0, mmMMVM_L2_CNTL); in mmhub_v2_0_init_cache_regs()
298 tmp = RREG32_SOC15(MMHUB, 0, mmMMVM_L2_CNTL2); in mmhub_v2_0_init_cache_regs()
329 tmp = RREG32_SOC15(MMHUB, 0, mmMMVM_CONTEXT0_CNTL); in mmhub_v2_0_enable_system_domain()
454 tmp = RREG32_SOC15(MMHUB, 0, mmMMMC_VM_MX_L1_TLB_CNTL); in mmhub_v2_0_gart_disable()
461 tmp = RREG32_SOC15(MMHUB, 0, mmMMVM_L2_CNTL); in mmhub_v2_0_gart_disable()
483 tmp = RREG32_SOC15(MMHUB, 0, mmMMVM_L2_PROTECTION_FAULT_CNTL); in mmhub_v2_0_set_fault_enable_default()
575 def1 = data1 = RREG32_SOC15(MMHUB, 0, mmDAGB0_CNTL_MISC2_Sienna_Cichlid); in mmhub_v2_0_update_medium_grain_clock_gating()
578 def = data = RREG32_SOC15(MMHUB, 0, mmMM_ATC_L2_MISC_CG); in mmhub_v2_0_update_medium_grain_clock_gating()
[all …]
H A Dmmhub_v3_3.c199 tmp = RREG32_SOC15(MMHUB, 0, regMMVM_L2_PROTECTION_FAULT_CNTL2); in mmhub_v3_3_init_system_aperture_regs()
210 tmp = RREG32_SOC15(MMHUB, 0, regMMMC_VM_MX_L1_TLB_CNTL); in mmhub_v3_3_init_tlb_regs()
230 tmp = RREG32_SOC15(MMHUB, 0, regMMVM_L2_CNTL); in mmhub_v3_3_init_cache_regs()
243 tmp = RREG32_SOC15(MMHUB, 0, regMMVM_L2_CNTL2); in mmhub_v3_3_init_cache_regs()
274 tmp = RREG32_SOC15(MMHUB, 0, regMMVM_CONTEXT0_CNTL); in mmhub_v3_3_enable_system_domain()
387 tmp = RREG32_SOC15(MMHUB, 0, regMMVM_L2_SAW_CONTEXT0_CNTL); in mmhub_v3_3_init_saw_regs()
397 tmp = RREG32_SOC15(MMHUB, 0, regMMVM_L2_SAW_CNTL4); in mmhub_v3_3_init_saw_regs()
443 tmp = RREG32_SOC15(MMHUB, 0, regMMMC_VM_MX_L1_TLB_CNTL); in mmhub_v3_3_gart_disable()
450 tmp = RREG32_SOC15(MMHUB, 0, regMMVM_L2_CNTL); in mmhub_v3_3_gart_disable()
467 tmp = RREG32_SOC15(MMHUB, 0, regMMVM_L2_PROTECTION_FAULT_CNTL); in mmhub_v3_3_set_fault_enable_default()
[all …]
H A Dmmhub_v4_1_0.c205 tmp = RREG32_SOC15(MMHUB, 0, regMMVM_L2_PROTECTION_FAULT_CNTL2); in mmhub_v4_1_0_init_system_aperture_regs()
216 tmp = RREG32_SOC15(MMHUB, 0, regMMMC_VM_MX_L1_TLB_CNTL); in mmhub_v4_1_0_init_tlb_regs()
242 tmp = RREG32_SOC15(MMHUB, 0, regMMVM_L2_CNTL); in mmhub_v4_1_0_init_cache_regs()
255 tmp = RREG32_SOC15(MMHUB, 0, regMMVM_L2_CNTL2); in mmhub_v4_1_0_init_cache_regs()
286 tmp = RREG32_SOC15(MMHUB, 0, regMMVM_CONTEXT0_CNTL); in mmhub_v4_1_0_enable_system_domain()
411 tmp = RREG32_SOC15(MMHUB, 0, regMMMC_VM_MX_L1_TLB_CNTL); in mmhub_v4_1_0_gart_disable()
418 tmp = RREG32_SOC15(MMHUB, 0, regMMVM_L2_CNTL); in mmhub_v4_1_0_gart_disable()
441 tmp = RREG32_SOC15(MMHUB, 0, regMMVM_L2_PROTECTION_FAULT_CNTL); in mmhub_v4_1_0_set_fault_enable_default()
531 base = RREG32_SOC15(MMHUB, 0, regMMMC_VM_FB_LOCATION_BASE); in mmhub_v4_1_0_get_fb_location()
541 return (u64)RREG32_SOC15(MMHUB, 0, regMMMC_VM_FB_OFFSET) << 24; in mmhub_v4_1_0_get_mc_fb_offset()
[all …]
H A Dgfx_v11_0.c959 return RREG32_SOC15(GC, 0, regSQ_IND_DATA); in wave_read_ind()
972 *(out++) = RREG32_SOC15(GC, 0, regSQ_IND_DATA); in wave_read_regs()
1853 gc_disabled_sa_mask = RREG32_SOC15(GC, 0, regCC_GC_SA_UNIT_DISABLE); in gfx_v11_0_get_sa_active_bitmap()
1857 gc_user_disabled_sa_mask = RREG32_SOC15(GC, 0, regGC_USER_SA_UNIT_DISABLE); in gfx_v11_0_get_sa_active_bitmap()
1872 gc_disabled_rb_mask = RREG32_SOC15(GC, 0, regCC_RB_BACKEND_DISABLE); in gfx_v11_0_get_rb_active_bitmap()
1876 gc_user_disabled_rb_mask = RREG32_SOC15(GC, 0, regGC_USER_RB_BACKEND_DISABLE); in gfx_v11_0_get_rb_active_bitmap()
1942 data = RREG32_SOC15(GC, 0, regSPI_GDBG_PER_VMID_CNTL); in gfx_v11_0_init_compute_vmid()
1987 uint32_t tcc_disable = RREG32_SOC15(GC, 0, regCGTS_TCC_DISABLE) | in gfx_v11_0_get_tcc_info()
1988 RREG32_SOC15(GC, 0, regCGTS_USER_TCC_DISABLE); in gfx_v11_0_get_tcc_info()
2009 tmp = RREG32_SOC15(GC, 0, regTA_CNTL2); in gfx_v11_0_constants_init()
[all …]
H A Dvcn_v1_0.c283 RREG32_SOC15(VCN, 0, mmUVD_STATUS))) { in vcn_v1_0_hw_fini()
496 data = RREG32_SOC15(VCN, 0, mmJPEG_CGC_CTRL); in vcn_v1_0_disable_clock_gating()
507 data = RREG32_SOC15(VCN, 0, mmJPEG_CGC_GATE); in vcn_v1_0_disable_clock_gating()
512 data = RREG32_SOC15(VCN, 0, mmUVD_CGC_CTRL); in vcn_v1_0_disable_clock_gating()
522 data = RREG32_SOC15(VCN, 0, mmUVD_CGC_GATE); in vcn_v1_0_disable_clock_gating()
545 data = RREG32_SOC15(VCN, 0, mmUVD_CGC_CTRL); in vcn_v1_0_disable_clock_gating()
569 data = RREG32_SOC15(VCN, 0, mmUVD_SUVD_CGC_GATE); in vcn_v1_0_disable_clock_gating()
596 data = RREG32_SOC15(VCN, 0, mmUVD_SUVD_CGC_CTRL); in vcn_v1_0_disable_clock_gating()
622 data = RREG32_SOC15(VCN, 0, mmJPEG_CGC_CTRL); in vcn_v1_0_enable_clock_gating()
631 data = RREG32_SOC15(VCN, 0, mmJPEG_CGC_GATE); in vcn_v1_0_enable_clock_gating()
[all …]
H A Dgfxhub_v1_1.c53 xgmi_lfb_cntl = RREG32_SOC15(GC, 0, mmMC_VM_XGMI_LFB_CNTL_ALDE); in gfxhub_v1_1_get_xgmi_info()
55 RREG32_SOC15(GC, 0, mmMC_VM_XGMI_LFB_SIZE_ALDE), in gfxhub_v1_1_get_xgmi_info()
60 xgmi_lfb_cntl = RREG32_SOC15(GC, 0, mmMC_VM_XGMI_LFB_CNTL); in gfxhub_v1_1_get_xgmi_info()
62 RREG32_SOC15(GC, 0, mmMC_VM_XGMI_LFB_SIZE), in gfxhub_v1_1_get_xgmi_info()
H A Dmmhub_v3_0_1.c203 tmp = RREG32_SOC15(MMHUB, 0, regMMVM_L2_PROTECTION_FAULT_CNTL2); in mmhub_v3_0_1_init_system_aperture_regs()
214 tmp = RREG32_SOC15(MMHUB, 0, regMMMC_VM_MX_L1_TLB_CNTL); in mmhub_v3_0_1_init_tlb_regs()
234 tmp = RREG32_SOC15(MMHUB, 0, regMMVM_L2_CNTL); in mmhub_v3_0_1_init_cache_regs()
247 tmp = RREG32_SOC15(MMHUB, 0, regMMVM_L2_CNTL2); in mmhub_v3_0_1_init_cache_regs()
278 tmp = RREG32_SOC15(MMHUB, 0, regMMVM_CONTEXT0_CNTL); in mmhub_v3_0_1_enable_system_domain()
397 tmp = RREG32_SOC15(MMHUB, 0, regMMMC_VM_MX_L1_TLB_CNTL); in mmhub_v3_0_1_gart_disable()
404 tmp = RREG32_SOC15(MMHUB, 0, regMMVM_L2_CNTL); in mmhub_v3_0_1_gart_disable()
421 tmp = RREG32_SOC15(MMHUB, 0, regMMVM_L2_PROTECTION_FAULT_CNTL); in mmhub_v3_0_1_set_fault_enable_default()
505 base = RREG32_SOC15(MMHUB, 0, regMMMC_VM_FB_LOCATION_BASE); in mmhub_v3_0_1_get_fb_location()
514 return (u64)RREG32_SOC15(MMHUB, 0, regMMMC_VM_FB_OFFSET) << 24; in mmhub_v3_0_1_get_mc_fb_offset()
[all …]
H A Dnbio_v2_3.c87 tmp = RREG32_SOC15(NBIO, 0, mmRCC_DEV0_EPF0_STRAP0); in nbio_v2_3_get_rev_id()
106 return RREG32_SOC15(NBIO, 0, mmRCC_DEV0_EPF0_RCC_CONFIG_MEMSIZE); in nbio_v2_3_get_memsize()
190 u32 ih_doorbell_range = RREG32_SOC15(NBIO, 0, mmBIF_IH_DOORBELL_RANGE); in nbio_v2_3_ih_doorbell_range()
214 interrupt_cntl = RREG32_SOC15(NBIO, 0, mmINTERRUPT_CNTL); in nbio_v2_3_ih_control()
387 def = data = RREG32_SOC15(NBIO, 0, mmRCC_BIF_STRAP2); in nbio_v2_3_program_ltr()
431 def = data = RREG32_SOC15(NBIO, 0, mmRCC_BIF_STRAP3); in nbio_v2_3_program_aspm()
437 def = data = RREG32_SOC15(NBIO, 0, mmRCC_BIF_STRAP5); in nbio_v2_3_program_aspm()
467 def = data = RREG32_SOC15(NBIO, 0, mmRCC_BIF_STRAP3); in nbio_v2_3_program_aspm()
473 def = data = RREG32_SOC15(NBIO, 0, mmRCC_BIF_STRAP5); in nbio_v2_3_program_aspm()
539 reg = RREG32_SOC15(NBIO, 0, mmBIF_RB_CNTL); in nbio_v2_3_clear_doorbell_interrupt()
[all …]
/linux/drivers/gpu/drm/amd/pm/powerplay/hwmgr/
H A Dvega10_thermal.c74 duty100 = REG_GET_FIELD(RREG32_SOC15(THM, 0, mmCG_FDO_CTRL1), in vega10_fan_ctrl_get_fan_speed_pwm()
76 duty = REG_GET_FIELD(RREG32_SOC15(THM, 0, mmCG_THERMAL_STATUS), in vega10_fan_ctrl_get_fan_speed_pwm()
104 REG_GET_FIELD(RREG32_SOC15(THM, 0, mmCG_TACH_STATUS), in vega10_fan_ctrl_get_fan_speed_rpm()
132 REG_GET_FIELD(RREG32_SOC15(THM, 0, mmCG_FDO_CTRL2), in vega10_fan_ctrl_set_static_mode()
135 REG_GET_FIELD(RREG32_SOC15(THM, 0, mmCG_FDO_CTRL2), in vega10_fan_ctrl_set_static_mode()
141 REG_SET_FIELD(RREG32_SOC15(THM, 0, mmCG_FDO_CTRL2), in vega10_fan_ctrl_set_static_mode()
144 REG_SET_FIELD(RREG32_SOC15(THM, 0, mmCG_FDO_CTRL2), in vega10_fan_ctrl_set_static_mode()
161 REG_SET_FIELD(RREG32_SOC15(THM, 0, mmCG_FDO_CTRL2), in vega10_fan_ctrl_set_default_mode()
165 REG_SET_FIELD(RREG32_SOC15(THM, 0, mmCG_FDO_CTRL2), in vega10_fan_ctrl_set_default_mode()
263 duty100 = REG_GET_FIELD(RREG32_SOC15(THM, 0, mmCG_FDO_CTRL1), in vega10_fan_ctrl_set_fan_speed_pwm()
[all …]
H A Dvega20_thermal.c95 REG_SET_FIELD(RREG32_SOC15(THM, 0, mmCG_FDO_CTRL2), in vega20_fan_ctrl_set_static_mode()
98 REG_SET_FIELD(RREG32_SOC15(THM, 0, mmCG_FDO_CTRL2), in vega20_fan_ctrl_set_static_mode()
124 duty100 = REG_GET_FIELD(RREG32_SOC15(THM, 0, mmCG_FDO_CTRL1), in vega20_fan_ctrl_get_fan_speed_pwm()
126 duty = REG_GET_FIELD(RREG32_SOC15(THM, 0, mmCG_THERMAL_STATUS), in vega20_fan_ctrl_get_fan_speed_pwm()
152 duty100 = REG_GET_FIELD(RREG32_SOC15(THM, 0, mmCG_FDO_CTRL1), in vega20_fan_ctrl_set_fan_speed_pwm()
163 REG_SET_FIELD(RREG32_SOC15(THM, 0, mmCG_FDO_CTRL0), in vega20_fan_ctrl_set_fan_speed_pwm()
206 REG_SET_FIELD(RREG32_SOC15(THM, 0, mmCG_TACH_CTRL), in vega20_fan_ctrl_set_fan_speed_rpm()
223 temp = RREG32_SOC15(THM, 0, mmCG_MULT_THERMAL_STATUS); in vega20_thermal_get_temperature()
260 val = RREG32_SOC15(THM, 0, mmTHM_THERMAL_INT_CTRL); in vega20_thermal_set_temperature_range()
/linux/drivers/gpu/drm/amd/pm/powerplay/smumgr/
H A Dsmu9_smumgr.c74 return RREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_103); in smu9_wait_for_response()
83 return RREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_90); in smu9_wait_for_response()
171 return RREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_102); in smu9_get_argument()
173 return RREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_82); in smu9_get_argument()

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