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Searched refs:RREG32_SOC15 (Results 1 – 25 of 81) sorted by relevance

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/linux/drivers/gpu/drm/amd/amdgpu/
H A Dimu_v12_0.c130 imu_reg_val = RREG32_SOC15(GC, 0, regGFX_IMU_GFX_RESET_CTRL); in imu_v12_0_wait_for_reset_status()
152 imu_reg_val = RREG32_SOC15(GC, 0, regGFX_IMU_C2PMSG_16); in imu_v12_0_setup()
156 imu_reg_val = RREG32_SOC15(GC, 0, regGFX_IMU_SCRATCH_10); in imu_v12_0_setup()
167 imu_reg_val = RREG32_SOC15(GC, 0, regGFX_IMU_CORE_CTRL); in imu_v12_0_start()
309 return RREG32_SOC15(MMHUB, 0, regMMMC_VM_FB_LOCATION_BASE); in imu_v12_init_gfxhub_settings()
311 return RREG32_SOC15(MMHUB, 0, regMMMC_VM_FB_LOCATION_TOP); in imu_v12_init_gfxhub_settings()
313 return RREG32_SOC15(MMHUB, 0, regMMMC_VM_FB_OFFSET); in imu_v12_init_gfxhub_settings()
315 return RREG32_SOC15(MMHUB, 0, regMMMC_VM_AGP_BASE); in imu_v12_init_gfxhub_settings()
317 return RREG32_SOC15(MMHUB, 0, regMMMC_VM_AGP_BOT); in imu_v12_init_gfxhub_settings()
319 return RREG32_SOC15(MMHUB, 0, regMMMC_VM_AGP_TOP); in imu_v12_init_gfxhub_settings()
[all …]
H A Dsmuio_v13_0.c48 def = data = RREG32_SOC15(SMUIO, 0, regCGTT_ROM_CLK_CTRL0); in smuio_v13_0_update_rom_clock_gating()
69 data = RREG32_SOC15(SMUIO, 0, regCGTT_ROM_CLK_CTRL0); in smuio_v13_0_get_clock_gating_state()
85 data = RREG32_SOC15(SMUIO, 0, regSMUIO_MCM_CONFIG); in smuio_v13_0_get_die_id()
102 data = RREG32_SOC15(SMUIO, 0, regSMUIO_MCM_CONFIG); in smuio_v13_0_get_socket_id()
119 data = RREG32_SOC15(SMUIO, 0, regSMUIO_MCM_CONFIG); in smuio_v13_0_is_host_gpu_xgmi_supported()
136 data = RREG32_SOC15(SMUIO, 0, regSMUIO_MCM_CONFIG); in smuio_v13_0_get_pkg_type()
H A Dumsch_mm_v4_0.c72 data = RREG32_SOC15(VCN, 0, regUMSCH_MES_RESET_CTRL); in umsch_mm_v4_0_load_microcode()
76 data = RREG32_SOC15(VCN, 0, regVCN_MES_CNTL); in umsch_mm_v4_0_load_microcode()
83 data = RREG32_SOC15(VCN, 0, regVCN_MES_IC_BASE_CNTL); in umsch_mm_v4_0_load_microcode()
129 data = RREG32_SOC15(VCN, 0, regUVD_UMSCH_FORCE); in umsch_mm_v4_0_load_microcode()
134 data = RREG32_SOC15(VCN, 0, regVCN_MES_IC_OP_CNTL); in umsch_mm_v4_0_load_microcode()
139 data = RREG32_SOC15(VCN, 0, regVCN_MES_IC_OP_CNTL); in umsch_mm_v4_0_load_microcode()
154 data = RREG32_SOC15(VCN, 0, regVCN_MES_CNTL); in umsch_mm_v4_0_load_microcode()
167 RREG32_SOC15(VCN, 0, regVCN_MES_MSTATUS_LO)); in umsch_mm_v4_0_load_microcode()
189 data = RREG32_SOC15(VCN, 0, regVCN_AGDB_CTRL0); in umsch_mm_v4_0_aggregated_doorbell_init()
195 data = RREG32_SOC15(VCN, 0, regVCN_AGDB_CTRL1); in umsch_mm_v4_0_aggregated_doorbell_init()
[all …]
H A Dmmhub_v2_3.c180 tmp = RREG32_SOC15(MMHUB, 0, mmMMVM_L2_PROTECTION_FAULT_CNTL2); in mmhub_v2_3_init_system_aperture_regs()
191 tmp = RREG32_SOC15(MMHUB, 0, mmMMMC_VM_MX_L1_TLB_CNTL); in mmhub_v2_3_init_tlb_regs()
210 tmp = RREG32_SOC15(MMHUB, 0, mmMMVM_L2_CNTL); in mmhub_v2_3_init_cache_regs()
223 tmp = RREG32_SOC15(MMHUB, 0, mmMMVM_L2_CNTL2); in mmhub_v2_3_init_cache_regs()
254 tmp = RREG32_SOC15(MMHUB, 0, mmMMVM_CONTEXT0_CNTL); in mmhub_v2_3_enable_system_domain()
387 tmp = RREG32_SOC15(MMHUB, 0, mmMMMC_VM_MX_L1_TLB_CNTL); in mmhub_v2_3_gart_disable()
394 tmp = RREG32_SOC15(MMHUB, 0, mmMMVM_L2_CNTL); in mmhub_v2_3_gart_disable()
411 tmp = RREG32_SOC15(MMHUB, 0, mmMMVM_L2_PROTECTION_FAULT_CNTL); in mmhub_v2_3_set_fault_enable_default()
498 def = data = RREG32_SOC15(MMHUB, 0, mmMM_ATC_L2_CGTT_CLK_CTRL); in mmhub_v2_3_update_medium_grain_clock_gating()
499 def1 = data1 = RREG32_SOC15(MMHUB, 0, mmDAGB0_CNTL_MISC2); in mmhub_v2_3_update_medium_grain_clock_gating()
[all …]
H A Dvcn_v4_0_5.c334 RREG32_SOC15(VCN, i, regUVD_STATUS))) { in vcn_v4_0_5_hw_fini()
620 data = RREG32_SOC15(VCN, inst, regUVD_POWER_STATUS); in vcn_v4_0_5_disable_static_power_gating()
643 data = RREG32_SOC15(VCN, inst, regUVD_POWER_STATUS); in vcn_v4_0_5_enable_static_power_gating()
688 data = RREG32_SOC15(VCN, inst, regUVD_CGC_CTRL); in vcn_v4_0_5_disable_clock_gating()
694 data = RREG32_SOC15(VCN, inst, regUVD_CGC_GATE); in vcn_v4_0_5_disable_clock_gating()
719 data = RREG32_SOC15(VCN, inst, regUVD_CGC_CTRL); in vcn_v4_0_5_disable_clock_gating()
742 data = RREG32_SOC15(VCN, inst, regUVD_SUVD_CGC_GATE); in vcn_v4_0_5_disable_clock_gating()
769 data = RREG32_SOC15(VCN, inst, regUVD_SUVD_CGC_CTRL); in vcn_v4_0_5_disable_clock_gating()
859 data = RREG32_SOC15(VCN, inst, regUVD_CGC_CTRL); in vcn_v4_0_5_enable_clock_gating()
865 data = RREG32_SOC15(VCN, inst, regUVD_CGC_CTRL); in vcn_v4_0_5_enable_clock_gating()
[all …]
H A Dsmuio_v14_0_2.c45 clock_counter_hi_pre = (u64)RREG32_SOC15(SMUIO, 0, regGOLDEN_TSC_COUNT_UPPER); in smuio_v14_0_2_get_gpu_clock_counter()
46 clock_counter_lo = (u64)RREG32_SOC15(SMUIO, 0, regGOLDEN_TSC_COUNT_LOWER); in smuio_v14_0_2_get_gpu_clock_counter()
48 clock_counter_hi_after = (u64)RREG32_SOC15(SMUIO, 0, regGOLDEN_TSC_COUNT_UPPER); in smuio_v14_0_2_get_gpu_clock_counter()
50 clock_counter_lo = (u64)RREG32_SOC15(SMUIO, 0, regGOLDEN_TSC_COUNT_LOWER); in smuio_v14_0_2_get_gpu_clock_counter()
H A Ddf_v1_7.c49 tmp = RREG32_SOC15(DF, 0, mmFabricConfigAccessControl); in df_v1_7_enable_broadcast_mode()
61 tmp = RREG32_SOC15(DF, 0, mmDF_CS_AON0_DramBaseAddress0); in df_v1_7_get_fb_channel_number()
88 tmp = RREG32_SOC15(DF, 0, mmDF_PIE_AON0_DfGlobalClkGater); in df_v1_7_update_medium_grain_clock_gating()
93 tmp = RREG32_SOC15(DF, 0, mmDF_PIE_AON0_DfGlobalClkGater); in df_v1_7_update_medium_grain_clock_gating()
109 tmp = RREG32_SOC15(DF, 0, mmDF_PIE_AON0_DfGlobalClkGater); in df_v1_7_get_clockgating_state()
H A Dmmhub_v3_0.c205 tmp = RREG32_SOC15(MMHUB, 0, regMMVM_L2_PROTECTION_FAULT_CNTL2); in mmhub_v3_0_init_system_aperture_regs()
216 tmp = RREG32_SOC15(MMHUB, 0, regMMMC_VM_MX_L1_TLB_CNTL); in mmhub_v3_0_init_tlb_regs()
242 tmp = RREG32_SOC15(MMHUB, 0, regMMVM_L2_CNTL); in mmhub_v3_0_init_cache_regs()
255 tmp = RREG32_SOC15(MMHUB, 0, regMMVM_L2_CNTL2); in mmhub_v3_0_init_cache_regs()
286 tmp = RREG32_SOC15(MMHUB, 0, regMMVM_CONTEXT0_CNTL); in mmhub_v3_0_enable_system_domain()
411 tmp = RREG32_SOC15(MMHUB, 0, regMMMC_VM_MX_L1_TLB_CNTL); in mmhub_v3_0_gart_disable()
418 tmp = RREG32_SOC15(MMHUB, 0, regMMVM_L2_CNTL); in mmhub_v3_0_gart_disable()
440 tmp = RREG32_SOC15(MMHUB, 0, regMMVM_L2_PROTECTION_FAULT_CNTL); in mmhub_v3_0_set_fault_enable_default()
530 base = RREG32_SOC15(MMHUB, 0, regMMMC_VM_FB_LOCATION_BASE); in mmhub_v3_0_get_fb_location()
540 return (u64)RREG32_SOC15(MMHUB, 0, regMMMC_VM_FB_OFFSET) << 24; in mmhub_v3_0_get_mc_fb_offset()
[all …]
H A Dmmhub_v4_1_0.c198 tmp = RREG32_SOC15(MMHUB, 0, regMMVM_L2_PROTECTION_FAULT_CNTL2); in mmhub_v4_1_0_init_system_aperture_regs()
209 tmp = RREG32_SOC15(MMHUB, 0, regMMMC_VM_MX_L1_TLB_CNTL); in mmhub_v4_1_0_init_tlb_regs()
235 tmp = RREG32_SOC15(MMHUB, 0, regMMVM_L2_CNTL); in mmhub_v4_1_0_init_cache_regs()
248 tmp = RREG32_SOC15(MMHUB, 0, regMMVM_L2_CNTL2); in mmhub_v4_1_0_init_cache_regs()
279 tmp = RREG32_SOC15(MMHUB, 0, regMMVM_CONTEXT0_CNTL); in mmhub_v4_1_0_enable_system_domain()
404 tmp = RREG32_SOC15(MMHUB, 0, regMMMC_VM_MX_L1_TLB_CNTL); in mmhub_v4_1_0_gart_disable()
411 tmp = RREG32_SOC15(MMHUB, 0, regMMVM_L2_CNTL); in mmhub_v4_1_0_gart_disable()
434 tmp = RREG32_SOC15(MMHUB, 0, regMMVM_L2_PROTECTION_FAULT_CNTL); in mmhub_v4_1_0_set_fault_enable_default()
524 base = RREG32_SOC15(MMHUB, 0, regMMMC_VM_FB_LOCATION_BASE); in mmhub_v4_1_0_get_fb_location()
534 return (u64)RREG32_SOC15(MMHUB, 0, regMMMC_VM_FB_OFFSET) << 24; in mmhub_v4_1_0_get_mc_fb_offset()
[all …]
H A Dmmhub_v2_0.c252 tmp = RREG32_SOC15(MMHUB, 0, mmMMVM_L2_PROTECTION_FAULT_CNTL2); in mmhub_v2_0_init_system_aperture_regs()
263 tmp = RREG32_SOC15(MMHUB, 0, mmMMMC_VM_MX_L1_TLB_CNTL); in mmhub_v2_0_init_tlb_regs()
288 tmp = RREG32_SOC15(MMHUB, 0, mmMMVM_L2_CNTL); in mmhub_v2_0_init_cache_regs()
301 tmp = RREG32_SOC15(MMHUB, 0, mmMMVM_L2_CNTL2); in mmhub_v2_0_init_cache_regs()
332 tmp = RREG32_SOC15(MMHUB, 0, mmMMVM_CONTEXT0_CNTL); in mmhub_v2_0_enable_system_domain()
457 tmp = RREG32_SOC15(MMHUB, 0, mmMMMC_VM_MX_L1_TLB_CNTL); in mmhub_v2_0_gart_disable()
464 tmp = RREG32_SOC15(MMHUB, 0, mmMMVM_L2_CNTL); in mmhub_v2_0_gart_disable()
486 tmp = RREG32_SOC15(MMHUB, 0, mmMMVM_L2_PROTECTION_FAULT_CNTL); in mmhub_v2_0_set_fault_enable_default()
578 def1 = data1 = RREG32_SOC15(MMHUB, 0, mmDAGB0_CNTL_MISC2_Sienna_Cichlid); in mmhub_v2_0_update_medium_grain_clock_gating()
581 def = data = RREG32_SOC15(MMHUB, 0, mmMM_ATC_L2_MISC_CG); in mmhub_v2_0_update_medium_grain_clock_gating()
[all …]
H A Dvcn_v5_0_0.c298 RREG32_SOC15(VCN, i, regUVD_STATUS))) { in vcn_v5_0_0_hw_fini()
587 data = RREG32_SOC15(VCN, inst, regUVD_POWER_STATUS); in vcn_v5_0_0_disable_static_power_gating()
612 data = RREG32_SOC15(VCN, inst, regUVD_POWER_STATUS); in vcn_v5_0_0_enable_static_power_gating()
709 tmp = RREG32_SOC15(VCN, inst_idx, regUVD_POWER_STATUS); in vcn_v5_0_0_start_dpg_mode()
770 tmp = RREG32_SOC15(VCN, inst_idx, regVCN_RB_ENABLE); in vcn_v5_0_0_start_dpg_mode()
777 tmp = RREG32_SOC15(VCN, inst_idx, regUVD_RB_RPTR); in vcn_v5_0_0_start_dpg_mode()
779 ring->wptr = RREG32_SOC15(VCN, inst_idx, regUVD_RB_WPTR); in vcn_v5_0_0_start_dpg_mode()
781 tmp = RREG32_SOC15(VCN, inst_idx, regVCN_RB_ENABLE); in vcn_v5_0_0_start_dpg_mode()
793 RREG32_SOC15(VCN, inst_idx, regUVD_STATUS); in vcn_v5_0_0_start_dpg_mode()
829 tmp = RREG32_SOC15(VCN, i, regUVD_STATUS) | UVD_STATUS__UVD_BUSY; in vcn_v5_0_0_start()
[all …]
H A Dmmhub_v1_0.c39 u64 base = RREG32_SOC15(MMHUB, 0, mmMC_VM_FB_LOCATION_BASE); in mmhub_v1_0_get_fb_location()
40 u64 top = RREG32_SOC15(MMHUB, 0, mmMC_VM_FB_LOCATION_TOP); in mmhub_v1_0_get_fb_location()
131 tmp = RREG32_SOC15(MMHUB, 0, mmVM_L2_PROTECTION_FAULT_CNTL2); in mmhub_v1_0_init_system_aperture_regs()
142 tmp = RREG32_SOC15(MMHUB, 0, mmMC_VM_MX_L1_TLB_CNTL); in mmhub_v1_0_init_tlb_regs()
165 tmp = RREG32_SOC15(MMHUB, 0, mmVM_L2_CNTL); in mmhub_v1_0_init_cache_regs()
176 tmp = RREG32_SOC15(MMHUB, 0, mmVM_L2_CNTL2); in mmhub_v1_0_init_cache_regs()
203 tmp = RREG32_SOC15(MMHUB, 0, mmVM_CONTEXT0_CNTL); in mmhub_v1_0_enable_system_domain()
262 tmp = RREG32_SOC15(MMHUB, 0, mmVM_L2_SAW_CONTEXT0_CNTL); in mmhub_v1_0_init_saw()
272 tmp = RREG32_SOC15(MMHUB, 0, mmVM_L2_SAW_CNTL4); in mmhub_v1_0_init_saw()
402 tmp = RREG32_SOC15(MMHUB, 0, mmMC_VM_MX_L1_TLB_CNTL); in mmhub_v1_0_gart_disable()
[all …]
H A Dhdp_v5_0.c53 hdp_clk_cntl = hdp_clk_cntl1 = RREG32_SOC15(HDP, 0, mmHDP_CLK_CNTL); in hdp_v5_0_update_mem_power_gating()
54 hdp_mem_pwr_cntl = RREG32_SOC15(HDP, 0, mmHDP_MEM_POWER_CTRL); in hdp_v5_0_update_mem_power_gating()
144 hdp_clk_cntl = RREG32_SOC15(HDP, 0, mmHDP_CLK_CNTL); in hdp_v5_0_update_medium_grain_clock_gating()
180 tmp = RREG32_SOC15(HDP, 0, mmHDP_CLK_CNTL); in hdp_v5_0_get_clockgating_state()
190 tmp = RREG32_SOC15(HDP, 0, mmHDP_MEM_POWER_CTRL); in hdp_v5_0_get_clockgating_state()
203 tmp = RREG32_SOC15(HDP, 0, mmHDP_MISC_CNTL); in hdp_v5_0_init_registers()
H A Dmmhub_v3_0_1.c211 tmp = RREG32_SOC15(MMHUB, 0, regMMVM_L2_PROTECTION_FAULT_CNTL2); in mmhub_v3_0_1_init_system_aperture_regs()
222 tmp = RREG32_SOC15(MMHUB, 0, regMMMC_VM_MX_L1_TLB_CNTL); in mmhub_v3_0_1_init_tlb_regs()
242 tmp = RREG32_SOC15(MMHUB, 0, regMMVM_L2_CNTL); in mmhub_v3_0_1_init_cache_regs()
255 tmp = RREG32_SOC15(MMHUB, 0, regMMVM_L2_CNTL2); in mmhub_v3_0_1_init_cache_regs()
286 tmp = RREG32_SOC15(MMHUB, 0, regMMVM_CONTEXT0_CNTL); in mmhub_v3_0_1_enable_system_domain()
405 tmp = RREG32_SOC15(MMHUB, 0, regMMMC_VM_MX_L1_TLB_CNTL); in mmhub_v3_0_1_gart_disable()
412 tmp = RREG32_SOC15(MMHUB, 0, regMMVM_L2_CNTL); in mmhub_v3_0_1_gart_disable()
429 tmp = RREG32_SOC15(MMHUB, 0, regMMVM_L2_PROTECTION_FAULT_CNTL); in mmhub_v3_0_1_set_fault_enable_default()
513 base = RREG32_SOC15(MMHUB, 0, regMMMC_VM_FB_LOCATION_BASE); in mmhub_v3_0_1_get_fb_location()
522 return (u64)RREG32_SOC15(MMHUB, 0, regMMMC_VM_FB_OFFSET) << 24; in mmhub_v3_0_1_get_mc_fb_offset()
[all …]
H A Dgfxhub_v1_1.c53 xgmi_lfb_cntl = RREG32_SOC15(GC, 0, mmMC_VM_XGMI_LFB_CNTL_ALDE); in gfxhub_v1_1_get_xgmi_info()
55 RREG32_SOC15(GC, 0, mmMC_VM_XGMI_LFB_SIZE_ALDE), in gfxhub_v1_1_get_xgmi_info()
60 xgmi_lfb_cntl = RREG32_SOC15(GC, 0, mmMC_VM_XGMI_LFB_CNTL); in gfxhub_v1_1_get_xgmi_info()
62 RREG32_SOC15(GC, 0, mmMC_VM_XGMI_LFB_SIZE), in gfxhub_v1_1_get_xgmi_info()
H A Dhdp_v5_2.c65 hdp_clk_cntl = RREG32_SOC15(HDP, 0, regHDP_CLK_CNTL); in hdp_v5_2_update_mem_power_gating()
66 hdp_mem_pwr_cntl = RREG32_SOC15(HDP, 0, regHDP_MEM_POWER_CTRL); in hdp_v5_2_update_mem_power_gating()
147 hdp_clk_cntl = RREG32_SOC15(HDP, 0, regHDP_CLK_CNTL); in hdp_v5_2_update_medium_grain_clock_gating()
176 tmp = RREG32_SOC15(HDP, 0, regHDP_CLK_CNTL); in hdp_v5_2_get_clockgating_state()
186 tmp = RREG32_SOC15(HDP, 0, regHDP_MEM_POWER_CTRL); in hdp_v5_2_get_clockgating_state()
H A Dsmuio_v13_0_3.c42 data = RREG32_SOC15(SMUIO, 0, regSMUIO_MCM_CONFIG); in smuio_v13_0_3_get_die_id()
59 data = RREG32_SOC15(SMUIO, 0, regSMUIO_MCM_CONFIG); in smuio_v13_0_3_get_socket_id()
78 data = RREG32_SOC15(SMUIO, 0, regSMUIO_MCM_CONFIG); in smuio_v13_0_3_get_pkg_type()
H A Dhdp_v6_0.c45 hdp_clk_cntl = RREG32_SOC15(HDP, 0, regHDP_CLK_CNTL_V6_1); in hdp_v6_0_update_clock_gating()
47 hdp_clk_cntl = RREG32_SOC15(HDP, 0, regHDP_CLK_CNTL); in hdp_v6_0_update_clock_gating()
48 hdp_mem_pwr_cntl = RREG32_SOC15(HDP, 0, regHDP_MEM_POWER_CTRL); in hdp_v6_0_update_clock_gating()
131 tmp = RREG32_SOC15(HDP, 0, regHDP_MEM_POWER_CTRL); in hdp_v6_0_get_clockgating_state()
H A Dvcn_v2_5.c239 harvest = RREG32_SOC15(VCN, i, mmCC_UVD_HARVESTING); in vcn_v2_5_early_init()
521 RREG32_SOC15(VCN, i, mmUVD_STATUS))) in vcn_v2_5_hw_fini()
759 data = RREG32_SOC15(VCN, i, mmUVD_CGC_CTRL); in vcn_v2_5_disable_clock_gating()
768 data = RREG32_SOC15(VCN, i, mmUVD_CGC_GATE); in vcn_v2_5_disable_clock_gating()
794 data = RREG32_SOC15(VCN, i, mmUVD_CGC_CTRL); in vcn_v2_5_disable_clock_gating()
818 data = RREG32_SOC15(VCN, i, mmUVD_SUVD_CGC_GATE); in vcn_v2_5_disable_clock_gating()
845 data = RREG32_SOC15(VCN, i, mmUVD_SUVD_CGC_CTRL); in vcn_v2_5_disable_clock_gating()
925 data = RREG32_SOC15(VCN, i, mmUVD_CGC_CTRL); in vcn_v2_5_enable_clock_gating()
934 data = RREG32_SOC15(VCN, i, mmUVD_CGC_CTRL); in vcn_v2_5_enable_clock_gating()
956 data = RREG32_SOC15(VCN, i, mmUVD_SUVD_CGC_CTRL); in vcn_v2_5_enable_clock_gating()
[all …]
H A Dmmhub_v3_0_2.c197 tmp = RREG32_SOC15(MMHUB, 0, regMMVM_L2_PROTECTION_FAULT_CNTL2); in mmhub_v3_0_2_init_system_aperture_regs()
208 tmp = RREG32_SOC15(MMHUB, 0, regMMMC_VM_MX_L1_TLB_CNTL); in mmhub_v3_0_2_init_tlb_regs()
234 tmp = RREG32_SOC15(MMHUB, 0, regMMVM_L2_CNTL); in mmhub_v3_0_2_init_cache_regs()
247 tmp = RREG32_SOC15(MMHUB, 0, regMMVM_L2_CNTL2); in mmhub_v3_0_2_init_cache_regs()
278 tmp = RREG32_SOC15(MMHUB, 0, regMMVM_CONTEXT0_CNTL); in mmhub_v3_0_2_enable_system_domain()
403 tmp = RREG32_SOC15(MMHUB, 0, regMMMC_VM_MX_L1_TLB_CNTL); in mmhub_v3_0_2_gart_disable()
410 tmp = RREG32_SOC15(MMHUB, 0, regMMVM_L2_CNTL); in mmhub_v3_0_2_gart_disable()
432 tmp = RREG32_SOC15(MMHUB, 0, regMMVM_L2_PROTECTION_FAULT_CNTL); in mmhub_v3_0_2_set_fault_enable_default()
519 base = RREG32_SOC15(MMHUB, 0, regMMMC_VM_FB_LOCATION_BASE); in mmhub_v3_0_2_get_fb_location()
528 return (u64)RREG32_SOC15(MMHUB, 0, regMMMC_VM_FB_OFFSET) << 24; in mmhub_v3_0_2_get_mc_fb_offset()
H A Dathub_v2_1.c38 def = data = RREG32_SOC15(ATHUB, 0, mmATHUB_MISC_CNTL); in athub_v2_1_update_medium_grain_clock_gating()
55 def = data = RREG32_SOC15(ATHUB, 0, mmATHUB_MISC_CNTL); in athub_v2_1_update_medium_grain_light_sleep()
93 data = RREG32_SOC15(ATHUB, 0, mmATHUB_MISC_CNTL); in athub_v2_1_get_clockgating()
H A Dathub_v2_0.c42 def = data = RREG32_SOC15(ATHUB, 0, mmATHUB_MISC_CNTL); in athub_v2_0_update_medium_grain_clock_gating()
63 def = data = RREG32_SOC15(ATHUB, 0, mmATHUB_MISC_CNTL); in athub_v2_0_update_medium_grain_light_sleep()
101 data = RREG32_SOC15(ATHUB, 0, mmATHUB_MISC_CNTL); in athub_v2_0_get_clockgating()
H A Dmmhub_v4_2_0.c79 base = RREG32_SOC15(MMHUB, GET_INST(MMHUB, 0), in mmhub_v4_2_0_get_fb_location()
85 RREG32_SOC15(MMHUB, GET_INST(MMHUB, 0), in mmhub_v4_2_0_get_fb_location()
93 return (u64)RREG32_SOC15(MMHUB, GET_INST(MMHUB, 0), in mmhub_v4_2_0_get_mc_fb_offset()
246 tmp = RREG32_SOC15(MMHUB, GET_INST(MMHUB, i), in mmhub_v4_2_0_mid_init_system_aperture_regs()
297 tmp = RREG32_SOC15(MMHUB, GET_INST(MMHUB, i), in mmhub_v4_2_0_mid_init_tlb_regs()
329 tmp = RREG32_SOC15(MMHUB, GET_INST(MMHUB, i), regMMVM_L2_CNTL); in mmhub_v4_2_0_mid_init_cache_regs()
345 tmp = RREG32_SOC15(MMHUB, GET_INST(MMHUB, i), regMMVM_L2_CNTL2); in mmhub_v4_2_0_mid_init_cache_regs()
393 tmp = RREG32_SOC15(MMHUB, GET_INST(MMHUB, i), in mmhub_v4_2_0_mid_enable_system_domain()
560 tmp = RREG32_SOC15(MMHUB, GET_INST(MMHUB, j), in mmhub_v4_2_0_mid_gart_disable()
570 tmp = RREG32_SOC15(MMHUB, GET_INST(MMHUB, j), regMMVM_L2_CNTL); in mmhub_v4_2_0_mid_gart_disable()
[all …]
H A Dathub_v1_0.c37 def = data = RREG32_SOC15(ATHUB, 0, mmATHUB_MISC_CNTL); in athub_update_medium_grain_clock_gating()
53 def = data = RREG32_SOC15(ATHUB, 0, mmATHUB_MISC_CNTL); in athub_update_medium_grain_light_sleep()
98 data = RREG32_SOC15(ATHUB, 0, mmATHUB_MISC_CNTL); in athub_v1_0_get_clockgating()
/linux/drivers/gpu/drm/amd/pm/powerplay/smumgr/
H A Dsmu9_smumgr.c74 return RREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_103); in smu9_wait_for_response()
83 return RREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_90); in smu9_wait_for_response()
171 return RREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_102); in smu9_get_argument()
173 return RREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_82); in smu9_get_argument()

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