Searched refs:RING_MI_MODE (Results 1 – 5 of 5) sorted by relevance
| /linux/drivers/gpu/drm/xe/regs/ |
| H A D | xe_engine_regs.h | 79 #define RING_MI_MODE(base) XE_REG((base) + 0x9c) macro
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| /linux/drivers/gpu/drm/i915/gt/ |
| H A D | intel_engine_cs.c | 1628 const i915_reg_t mode = RING_MI_MODE(engine->mmio_base); in __intel_engine_stop_cs()
1695 ENGINE_WRITE_FW(engine, RING_MI_MODE, REG_MASKED_FIELD_DISABLE(STOP_RING)); in intel_engine_cancel_stop_cs()
1856 !(ENGINE_READ(engine, RING_MI_MODE) & MODE_IDLE)) in ring_is_idle()
2101 ENGINE_READ(engine, RING_MI_MODE), in intel_engine_print_registers()
2102 ENGINE_READ(engine, RING_MI_MODE) & (MODE_IDLE) ? " [idle]" : ""); in intel_engine_print_registers()
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| /linux/drivers/gpu/drm/xe/ |
| H A D | xe_hw_engine.c | 343 xe_hw_engine_mmio_write32(hwe, RING_MI_MODE(0), in xe_hw_engine_enable_ring()
345 xe_hw_engine_mmio_read32(hwe, RING_MI_MODE(0)); in xe_hw_engine_enable_ring()
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| /linux/drivers/gpu/drm/i915/ |
| H A D | i915_pmu.c | 386 val = ENGINE_READ_FW(engine, RING_MI_MODE); in gen3_engine_sample()
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| /linux/drivers/gpu/drm/i915/gt/uc/ |
| H A D | intel_guc_capture.c | 71 { RING_MI_MODE(0), 0, 0, "MODE" }, \
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