| /linux/drivers/gpu/drm/xe/regs/ |
| H A D | xe_engine_regs.h | 76 #define RING_MI_MODE(base) XE_REG((base) + 0x9c) macro
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| /linux/drivers/gpu/drm/i915/gvt/ |
| H A D | mmio_context.c | 82 {BCS0, RING_MI_MODE(BLT_RING_BASE), 0xffff, false}, /* 0x2209c */
136 {BCS0, RING_MI_MODE(BLT_RING_BASE), 0xffff, false}, /* 0x2209c */
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| H A D | handlers.c | 2235 MMIO_RING_DFH(RING_MI_MODE, D_ALL, F_MODE_MASK | F_CMD_ACCESS, in init_generic_mmio_info()
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| /linux/drivers/gpu/drm/i915/gt/ |
| H A D | intel_ring_submission.c | 122 if ((ENGINE_READ(engine, RING_MI_MODE) & MODE_IDLE) == 0) in flush_cs_tlb()
249 RING_MI_MODE, _MASKED_BIT_DISABLE(STOP_RING)); in xcs_resume()
1060 (ENGINE_READ(engine, RING_MI_MODE) & MODE_IDLE) == 0); in ring_release()
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| H A D | intel_engine_cs.c | 1631 const i915_reg_t mode = RING_MI_MODE(engine->mmio_base); in __intel_engine_stop_cs()
1698 ENGINE_WRITE_FW(engine, RING_MI_MODE, _MASKED_BIT_DISABLE(STOP_RING)); in intel_engine_cancel_stop_cs()
1859 !(ENGINE_READ(engine, RING_MI_MODE) & MODE_IDLE)) in ring_is_idle()
2103 ENGINE_READ(engine, RING_MI_MODE), in intel_engine_print_registers()
2104 ENGINE_READ(engine, RING_MI_MODE) & (MODE_IDLE) ? " [idle]" : ""); in intel_engine_print_registers()
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| H A D | intel_engine_regs.h | 73 #define RING_MI_MODE(base) _MMIO((base) + 0x9c) macro
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| H A D | intel_workarounds.c | 354 wa_masked_en(wal, RING_MI_MODE(RENDER_RING_BASE), ASYNC_FLIP_PERF_DISABLE); in gen8_ctx_workarounds_init()
858 wa_masked_dis(wal, RING_MI_MODE(engine->mmio_base), TGL_NESTED_BB_EN); in fakewa_disable_nestedbb_mode()
2587 RING_MI_MODE(RENDER_RING_BASE), in rcs_engine_wa_init()
2646 wa_add(wal, RING_MI_MODE(RENDER_RING_BASE), in rcs_engine_wa_init()
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| H A D | intel_execlists_submission.c | 1980 ENGINE_READ(engine, RING_MI_MODE)); in process_csb()
2945 ENGINE_WRITE_FW(engine, RING_MI_MODE, _MASKED_BIT_DISABLE(STOP_RING)); in enable_execlists()
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| H A D | selftest_lrc.c | 324 i915_mmio_reg_offset(RING_MI_MODE(engine->mmio_base)), in live_lrc_fixed()
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| /linux/drivers/gpu/drm/xe/ |
| H A D | xe_hw_engine.c | 335 xe_hw_engine_mmio_write32(hwe, RING_MI_MODE(0), in xe_hw_engine_enable_ring()
337 xe_hw_engine_mmio_read32(hwe, RING_MI_MODE(0)); in xe_hw_engine_enable_ring()
952 xe_hw_engine_mmio_read32(hwe, RING_MI_MODE(0)); in xe_hw_engine_snapshot_capture()
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| /linux/drivers/gpu/drm/i915/ |
| H A D | i915_pmu.c | 387 val = ENGINE_READ_FW(engine, RING_MI_MODE); in engine_sample()
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| H A D | intel_gvt_mmio_table.c | 95 MMIO_RING_D(RING_MI_MODE); in iterate_generic_mmio()
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| H A D | intel_uncore.c | 1751 __raw_uncore_write32(uncore, RING_MI_MODE(RENDER_RING_BASE), 0); in ilk_dummy_write()
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| H A D | i915_gpu_error.c | 1302 ee->mode = ENGINE_READ(engine, RING_MI_MODE); in engine_record_registers()
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| /linux/drivers/gpu/drm/i915/gt/uc/ |
| H A D | intel_guc_capture.c | 71 { RING_MI_MODE(0), 0, 0, "MODE" }, \
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| H A D | intel_guc_submission.c | 4352 ENGINE_WRITE_FW(engine, RING_MI_MODE, _MASKED_BIT_DISABLE(STOP_RING)); in start_engine()
4353 ENGINE_POSTING_READ(engine, RING_MI_MODE); in start_engine()
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