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Searched refs:RING_IMR (Results 1 – 6 of 6) sorted by relevance

/linux/drivers/gpu/drm/i915/gt/
H A Dgen6_engine_cs.c427 ENGINE_WRITE(engine, RING_IMR, in gen6_irq_enable()
431 ENGINE_POSTING_READ(engine, RING_IMR); in gen6_irq_enable()
438 ENGINE_WRITE(engine, RING_IMR, ~engine->irq_keep_mask); in gen6_irq_disable()
444 ENGINE_WRITE(engine, RING_IMR, ~engine->irq_enable_mask); in hsw_irq_enable_vecs()
447 ENGINE_POSTING_READ(engine, RING_IMR); in hsw_irq_enable_vecs()
454 ENGINE_WRITE(engine, RING_IMR, ~0); in hsw_irq_disable_vecs()
H A Dintel_engine_cs.c2107 ENGINE_READ(engine, RING_IMR)); in intel_engine_print_registers()
/linux/drivers/gpu/drm/xe/regs/
H A Dxe_engine_regs.h86 #define RING_IMR(base) XE_REG((base) + 0xa8) macro
/linux/drivers/gpu/drm/i915/gt/uc/
H A Dintel_guc_ads.c393 ret |= GUC_MMIO_REG_ADD(gt, regset, RING_IMR(base), false); in guc_mmio_regset_init()
/linux/drivers/gpu/drm/xe/
H A Dxe_guc_ads.c744 { .reg = RING_IMR(hwe->mmio_base), }, in guc_mmio_regset_write()
H A Dxe_lrc.c668 regs[CTX_INT_MASK_ENABLE_REG] = RING_IMR(0).addr; in set_memory_based_intr()