| /linux/include/dt-bindings/phy/ |
| H A D | phy-lan966x-serdes.h | 10 #define RGMII(x) (SERDES6G_MAX + 1 + (x)) macro
11 #define RGMII_MAX RGMII(2)
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| /linux/Documentation/devicetree/bindings/net/ |
| H A D | ibm,emac.txt | 5 special McMAL DMA controller, and sometimes an RGMII or ZMII
55 - rgmii-device : 1 cell, required iff connected to an RGMII. phandle
56 of the RGMII device node.
58 - rgmii-channel : 1 cell, required iff connected to an RGMII. Which
59 RGMII channel is used by this EMAC.
195 iv) RGMII node
203 - revision : as provided by the RGMII new version register if
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| H A D | cavium-pip.txt | 40 - rx-delay: Delay value for RGMII receive clock. Optional. Disabled if 0.
43 - tx-delay: Delay value for RGMII transmit clock. Optional. Disabled if 0.
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| H A D | snps,dwc-qos-ethernet.txt | 29 In some configurations (e.g. GMII/RGMII), this clock also drives the PHY TX
34 In some configurations (e.g. GMII/RGMII), this clock is derived from the
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| /linux/arch/arm64/boot/dts/freescale/ |
| H A D | fsl-lx2160a-bluebox3-rev-a.dts | 15 /* The RGMII PHYs have a different MDIO address */
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| H A D | s32g274a-evb.dts | 57 /* KSZ 9031 on RGMII */
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| H A D | fsl-ls1028a-kontron-sl28-var4.dts | 6 * extends the base and provides one more port connected via RGMII.
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| H A D | s32g399a-rdb3.dts | 107 /* KSZ 9031 on RGMII */
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| H A D | fsl-ls1028a-kontron-sl28-var1.dts | 7 * port is connected via RGMII. This port is not TSN aware.
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| H A D | s32g274a-rdb2.dts | 91 /* KSZ 9031 on RGMII */
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| /linux/arch/arm64/boot/dts/amlogic/ |
| H A D | meson-gxm-vega-s96.dts | 28 /* External PHY is in RGMII */
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| H A D | meson-gxm-ugoos-am3.dts | 50 /* External PHY is in RGMII */
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| H A D | meson-gxbb-nanopi-k2.dts | 251 "Eth MDIO", "Eth MDC", "Eth RGMII RX Clk",
253 "Eth RX D3", "Eth RGMII TX Clk", "Eth TX En",
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| H A D | meson-gxm-nexbox-a1.dts | 167 /* External PHY is in RGMII */
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| H A D | meson-gxm-rbox-pro.dts | 169 /* External PHY is in RGMII */
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| /linux/drivers/phy/microchip/ |
| H A D | lan966x_serdes.c | 101 SERDES_MUX_RGMII(RGMII(0), 2, HSIO_HW_CFG_RGMII_0_CFG |
107 SERDES_MUX_RGMII(RGMII(1), 3, HSIO_HW_CFG_RGMII_1_CFG |
113 SERDES_MUX_RGMII(RGMII(0), 5, HSIO_HW_CFG_RGMII_0_CFG |
119 SERDES_MUX_RGMII(RGMII(1), 6, HSIO_HW_CFG_RGMII_1_CFG |
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| /linux/arch/powerpc/boot/dts/ |
| H A D | kmeter1.dts | 314 /* ESTAR-1 (UCC1, MDIO 0x10, RGMII) */
330 /* ESTAR-2 (UCC2, MDIO 0x11, RGMII) */
457 /* ESTAR-1 (UCC1, MDIO 0x10, RGMII) */
464 /* ESTAR-2 (UCC2, MDIO 0x11, RGMII) */
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| H A D | fsp2.dts | 538 rgmii-device = <&RGMII>;
564 rgmii-device = <&RGMII>;
568 RGMII: rgmii@b0000600 { label
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| /linux/arch/riscv/boot/dts/starfive/ |
| H A D | jh7100-starfive-visionfive-v1.dts | 26 * The board uses a Motorcomm YT8521 PHY supporting RGMII-ID, but requires
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| /linux/arch/arm/boot/dts/microchip/ |
| H A D | at91-sama5d3_eds.dts | 211 /* Reserved for reset signal to the RGMII connector. */
217 /* Reserved for an interrupt line from the RMII and RGMII connectors. */
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| /linux/Documentation/networking/dsa/ |
| H A D | bcm_sf2.rst | 19 - several external MII/RevMII/GMII/RGMII interfaces
105 - turning off RGMII data processing logic when the link goes down
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| H A D | sja1105.rst | 358 RGMII fixed-link and internal delays
363 correct RGMII timing budget.
370 In RGMII the clock frequency changes with link speed (125 MHz at 1000 Mbps, 25
373 In the situation where the switch port is connected through an RGMII fixed-link
377 The take-away is that in RGMII mode, the switch's internal delays are only
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| /linux/arch/arm/boot/dts/nxp/imx/ |
| H A D | imx6qp-prtwd3.dts | 460 /* Configure clock provider for RGMII ref clock */
462 /* Configure clock consumer for RGMII ref clock */
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| /linux/arch/arm/boot/dts/st/ |
| H A D | stm32mp15xc-lxa-tac.dtsi | 187 /* Reduce EMI emission by reducing RGMII drive strength */
389 /* Reduce RGMII EMI emissions by reducing drive strength */
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| H A D | stm32mp151c-mect1s.dts | 246 /* RGMII mode is not working properly, using RMII instead. */
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