xref: /linux/arch/riscv/boot/dts/starfive/jh7100-starfive-visionfive-v1.dts (revision 79790b6818e96c58fe2bffee1b418c16e64e7b80)
1ab8ec079SCristian Ciocaltea// SPDX-License-Identifier: GPL-2.0 OR MIT
2ab8ec079SCristian Ciocaltea/*
3ab8ec079SCristian Ciocaltea * Copyright (C) 2021 StarFive Technology Co., Ltd.
4ab8ec079SCristian Ciocaltea * Copyright (C) 2021 Emil Renner Berthing <kernel@esmil.dk>
5ab8ec079SCristian Ciocaltea */
6ab8ec079SCristian Ciocaltea
7ab8ec079SCristian Ciocaltea/dts-v1/;
8ab8ec079SCristian Ciocaltea#include "jh7100-common.dtsi"
9ab8ec079SCristian Ciocaltea
10ab8ec079SCristian Ciocaltea/ {
11ab8ec079SCristian Ciocaltea	model = "StarFive VisionFive V1";
12ab8ec079SCristian Ciocaltea	compatible = "starfive,visionfive-v1", "starfive,jh7100";
13ab8ec079SCristian Ciocaltea
14ab8ec079SCristian Ciocaltea	gpio-restart {
15ab8ec079SCristian Ciocaltea		compatible = "gpio-restart";
16ab8ec079SCristian Ciocaltea		gpios = <&gpio 63 GPIO_ACTIVE_HIGH>;
17ab8ec079SCristian Ciocaltea		priority = <224>;
18ab8ec079SCristian Ciocaltea	};
19ab8ec079SCristian Ciocaltea};
20*e16d3dc0SCristian Ciocaltea
21*e16d3dc0SCristian Ciocaltea&gmac {
22*e16d3dc0SCristian Ciocaltea	phy-handle = <&phy>;
23*e16d3dc0SCristian Ciocaltea};
24*e16d3dc0SCristian Ciocaltea
25*e16d3dc0SCristian Ciocaltea/*
26*e16d3dc0SCristian Ciocaltea * The board uses a Motorcomm YT8521 PHY supporting RGMII-ID, but requires
27*e16d3dc0SCristian Ciocaltea * manual adjustment of the RX internal delay to work properly.  The default
28*e16d3dc0SCristian Ciocaltea * RX delay provided by the driver (1.95ns) is too high, but applying a 50%
29*e16d3dc0SCristian Ciocaltea * reduction seems to mitigate the issue.
30*e16d3dc0SCristian Ciocaltea *
31*e16d3dc0SCristian Ciocaltea * It is worth noting the adjustment is not necessary on BeagleV Starlight SBC,
32*e16d3dc0SCristian Ciocaltea * which uses a Microchip PHY.  Hence, most likely the Motorcomm PHY is the one
33*e16d3dc0SCristian Ciocaltea * responsible for the misbehaviour, not the GMAC.
34*e16d3dc0SCristian Ciocaltea */
35*e16d3dc0SCristian Ciocaltea&mdio {
36*e16d3dc0SCristian Ciocaltea	phy: ethernet-phy@0 {
37*e16d3dc0SCristian Ciocaltea		reg = <0>;
38*e16d3dc0SCristian Ciocaltea		rx-internal-delay-ps = <900>;
39*e16d3dc0SCristian Ciocaltea	};
40*e16d3dc0SCristian Ciocaltea};
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