13c91d114SIoana Ciornei============================================= 23c91d114SIoana CiorneiBroadcom Starfighter 2 Ethernet switch driver 33c91d114SIoana Ciornei============================================= 43c91d114SIoana Ciornei 53c91d114SIoana CiorneiBroadcom's Starfighter 2 Ethernet switch hardware block is commonly found and 63c91d114SIoana Ciorneideployed in the following products: 73c91d114SIoana Ciornei 83c91d114SIoana Ciornei- xDSL gateways such as BCM63138 93c91d114SIoana Ciornei- streaming/multimedia Set Top Box such as BCM7445 103c91d114SIoana Ciornei- Cable Modem/residential gateways such as BCM7145/BCM3390 113c91d114SIoana Ciornei 123c91d114SIoana CiorneiThe switch is typically deployed in a configuration involving between 5 to 13 133c91d114SIoana Ciorneiports, offering a range of built-in and customizable interfaces: 143c91d114SIoana Ciornei 153c91d114SIoana Ciornei- single integrated Gigabit PHY 163c91d114SIoana Ciornei- quad integrated Gigabit PHY 173c91d114SIoana Ciornei- quad external Gigabit PHY w/ MDIO multiplexer 183c91d114SIoana Ciornei- integrated MoCA PHY 193c91d114SIoana Ciornei- several external MII/RevMII/GMII/RGMII interfaces 203c91d114SIoana Ciornei 213c91d114SIoana CiorneiThe switch also supports specific congestion control features which allow MoCA 223c91d114SIoana Ciorneifail-over not to lose packets during a MoCA role re-election, as well as out of 233c91d114SIoana Ciorneiband back-pressure to the host CPU network interface when downstream interfaces 243c91d114SIoana Ciorneiare connected at a lower speed. 253c91d114SIoana Ciornei 263c91d114SIoana CiorneiThe switch hardware block is typically interfaced using MMIO accesses and 273c91d114SIoana Ciorneicontains a bunch of sub-blocks/registers: 283c91d114SIoana Ciornei 293c91d114SIoana Ciornei- ``SWITCH_CORE``: common switch registers 303c91d114SIoana Ciornei- ``SWITCH_REG``: external interfaces switch register 313c91d114SIoana Ciornei- ``SWITCH_MDIO``: external MDIO bus controller (there is another one in SWITCH_CORE, 323c91d114SIoana Ciornei which is used for indirect PHY accesses) 333c91d114SIoana Ciornei- ``SWITCH_INDIR_RW``: 64-bits wide register helper block 343c91d114SIoana Ciornei- ``SWITCH_INTRL2_0/1``: Level-2 interrupt controllers 353c91d114SIoana Ciornei- ``SWITCH_ACB``: Admission control block 363c91d114SIoana Ciornei- ``SWITCH_FCB``: Fail-over control block 373c91d114SIoana Ciornei 383c91d114SIoana CiorneiImplementation details 393c91d114SIoana Ciornei====================== 403c91d114SIoana Ciornei 413c91d114SIoana CiorneiThe driver is located in ``drivers/net/dsa/bcm_sf2.c`` and is implemented as a DSA 423c91d114SIoana Ciorneidriver; see ``Documentation/networking/dsa/dsa.rst`` for details on the subsystem 433c91d114SIoana Ciorneiand what it provides. 443c91d114SIoana Ciornei 453c91d114SIoana CiorneiThe SF2 switch is configured to enable a Broadcom specific 4-bytes switch tag 463c91d114SIoana Ciorneiwhich gets inserted by the switch for every packet forwarded to the CPU 473c91d114SIoana Ciorneiinterface, conversely, the CPU network interface should insert a similar tag for 483c91d114SIoana Ciorneipackets entering the CPU port. The tag format is described in 493c91d114SIoana Ciornei``net/dsa/tag_brcm.c``. 503c91d114SIoana Ciornei 513c91d114SIoana CiorneiOverall, the SF2 driver is a fairly regular DSA driver; there are a few 523c91d114SIoana Ciorneispecifics covered below. 533c91d114SIoana Ciornei 543c91d114SIoana CiorneiDevice Tree probing 553c91d114SIoana Ciornei------------------- 563c91d114SIoana Ciornei 573c91d114SIoana CiorneiThe DSA platform device driver is probed using a specific compatible string 583c91d114SIoana Ciorneiprovided in ``net/dsa/dsa.c``. The reason for that is because the DSA subsystem gets 593c91d114SIoana Ciorneiregistered as a platform device driver currently. DSA will provide the needed 603c91d114SIoana Ciorneidevice_node pointers which are then accessible by the switch driver setup 613c91d114SIoana Ciorneifunction to setup resources such as register ranges and interrupts. This 623c91d114SIoana Ciorneicurrently works very well because none of the of_* functions utilized by the 633c91d114SIoana Ciorneidriver require a struct device to be bound to a struct device_node, but things 643c91d114SIoana Ciorneimay change in the future. 653c91d114SIoana Ciornei 663c91d114SIoana CiorneiMDIO indirect accesses 673c91d114SIoana Ciornei---------------------- 683c91d114SIoana Ciornei 693c91d114SIoana CiorneiDue to a limitation in how Broadcom switches have been designed, external 70*6ca80638SFlorian FainelliBroadcom switches connected to a SF2 require the use of the DSA user MDIO bus 713c91d114SIoana Ciorneiin order to properly configure them. By default, the SF2 pseudo-PHY address, and 723c91d114SIoana Ciorneian external switch pseudo-PHY address will both be snooping for incoming MDIO 733c91d114SIoana Ciorneitransactions, since they are at the same address (30), resulting in some kind of 743c91d114SIoana Ciornei"double" programming. Using DSA, and setting ``ds->phys_mii_mask`` accordingly, we 753c91d114SIoana Ciorneiselectively divert reads and writes towards external Broadcom switches 763c91d114SIoana Ciorneipseudo-PHY addresses. Newer revisions of the SF2 hardware have introduced a 773c91d114SIoana Ciorneiconfigurable pseudo-PHY address which circumvents the initial design limitation. 783c91d114SIoana Ciornei 793c91d114SIoana CiorneiMultimedia over CoAxial (MoCA) interfaces 803c91d114SIoana Ciornei----------------------------------------- 813c91d114SIoana Ciornei 823c91d114SIoana CiorneiMoCA interfaces are fairly specific and require the use of a firmware blob which 833c91d114SIoana Ciorneigets loaded onto the MoCA processor(s) for packet processing. The switch 843c91d114SIoana Ciorneihardware contains logic which will assert/de-assert link states accordingly for 853c91d114SIoana Ciorneithe MoCA interface whenever the MoCA coaxial cable gets disconnected or the 863c91d114SIoana Ciorneifirmware gets reloaded. The SF2 driver relies on such events to properly set its 873c91d114SIoana CiorneiMoCA interface carrier state and properly report this to the networking stack. 883c91d114SIoana Ciornei 893c91d114SIoana CiorneiThe MoCA interfaces are supported using the PHY library's fixed PHY/emulated PHY 903c91d114SIoana Ciorneidevice and the switch driver registers a ``fixed_link_update`` callback for such 913c91d114SIoana CiorneiPHYs which reflects the link state obtained from the interrupt handler. 923c91d114SIoana Ciornei 933c91d114SIoana Ciornei 943c91d114SIoana CiorneiPower Management 953c91d114SIoana Ciornei---------------- 963c91d114SIoana Ciornei 973c91d114SIoana CiorneiWhenever possible, the SF2 driver tries to minimize the overall switch power 983c91d114SIoana Ciorneiconsumption by applying a combination of: 993c91d114SIoana Ciornei 1003c91d114SIoana Ciornei- turning off internal buffers/memories 1013c91d114SIoana Ciornei- disabling packet processing logic 1023c91d114SIoana Ciornei- putting integrated PHYs in IDDQ/low-power 1033c91d114SIoana Ciornei- reducing the switch core clock based on the active port count 1043c91d114SIoana Ciornei- enabling and advertising EEE 1053c91d114SIoana Ciornei- turning off RGMII data processing logic when the link goes down 1063c91d114SIoana Ciornei 1073c91d114SIoana CiorneiWake-on-LAN 1083c91d114SIoana Ciornei----------- 1093c91d114SIoana Ciornei 1103c91d114SIoana CiorneiWake-on-LAN is currently implemented by utilizing the host processor Ethernet 1113c91d114SIoana CiorneiMAC controller wake-on logic. Whenever Wake-on-LAN is requested, an intersection 1123c91d114SIoana Ciorneibetween the user request and the supported host Ethernet interface WoL 1133c91d114SIoana Ciorneicapabilities is done and the intersection result gets configured. During 1143c91d114SIoana Ciorneisystem-wide suspend/resume, only ports not participating in Wake-on-LAN are 1153c91d114SIoana Ciorneidisabled. 116