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Searched refs:REG_WRITE (Results 1 – 25 of 78) sorted by relevance

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/linux/drivers/net/wireless/ath/
H A Dkey.c26 #define REG_WRITE(_ah, _reg, _val) (common->ops->write)(_ah, _val, _reg) macro
57 REG_WRITE(ah, AR_KEYTABLE_KEY0(entry), 0); in ath_hw_keyreset()
58 REG_WRITE(ah, AR_KEYTABLE_KEY1(entry), 0); in ath_hw_keyreset()
59 REG_WRITE(ah, AR_KEYTABLE_KEY2(entry), 0); in ath_hw_keyreset()
60 REG_WRITE(ah, AR_KEYTABLE_KEY3(entry), 0); in ath_hw_keyreset()
61 REG_WRITE(ah, AR_KEYTABLE_KEY4(entry), 0); in ath_hw_keyreset()
62 REG_WRITE(ah, AR_KEYTABLE_TYPE(entry), AR_KEYTABLE_TYPE_CLR); in ath_hw_keyreset()
63 REG_WRITE(ah, AR_KEYTABLE_MAC0(entry), 0); in ath_hw_keyreset()
64 REG_WRITE(ah, AR_KEYTABLE_MAC1(entry), 0); in ath_hw_keyreset()
69 REG_WRITE(ah, AR_KEYTABLE_KEY0(micentry), 0); in ath_hw_keyreset()
[all …]
H A Dhw.c24 #define REG_WRITE(_ah, _reg, _val) (common->ops->write)(_ah, _val, _reg) macro
123 REG_WRITE(ah, AR_STA_ID0, get_unaligned_le32(common->macaddr)); in ath_hw_setbssidmask()
126 REG_WRITE(ah, AR_STA_ID1, id1); in ath_hw_setbssidmask()
128 REG_WRITE(ah, AR_BSSMSKL, get_unaligned_le32(common->bssidmask)); in ath_hw_setbssidmask()
129 REG_WRITE(ah, AR_BSSMSKU, get_unaligned_le16(common->bssidmask + 4)); in ath_hw_setbssidmask()
148 REG_WRITE(ah, AR_MIBC, AR_MIBC_FMC); in ath_hw_cycle_counters_update()
157 REG_WRITE(ah, AR_CCCNT, 0); in ath_hw_cycle_counters_update()
158 REG_WRITE(ah, AR_RFCNT, 0); in ath_hw_cycle_counters_update()
159 REG_WRITE(ah, AR_RCCNT, 0); in ath_hw_cycle_counters_update()
160 REG_WRITE(ah, AR_TFCNT, 0); in ath_hw_cycle_counters_update()
[all …]
/linux/drivers/gpu/drm/gma500/
H A Doaktrail_hdmi.c293 REG_WRITE(VGACNTRL, VGA_DISP_DISABLE); in oaktrail_crtc_hdmi_mode_set()
298 REG_WRITE(DPLL_CTRL, dpll | (DPLL_PWRDN | DPLL_RESET)); in oaktrail_crtc_hdmi_mode_set()
299 REG_WRITE(DPLL_DIV_CTRL, 0x00000000); in oaktrail_crtc_hdmi_mode_set()
300 REG_WRITE(DPLL_STATUS, 0x1); in oaktrail_crtc_hdmi_mode_set()
315 REG_WRITE(DPLL_CTRL, 0x00000008); in oaktrail_crtc_hdmi_mode_set()
316 REG_WRITE(DPLL_DIV_CTRL, ((clock.nf << 6) | clock.nr)); in oaktrail_crtc_hdmi_mode_set()
317 REG_WRITE(DPLL_ADJUST, ((clock.nf >> 14) - 1)); in oaktrail_crtc_hdmi_mode_set()
318 REG_WRITE(DPLL_CTRL, (dpll | (clock.np << DPLL_PDIV_SHIFT) | DPLL_ENSTAT | DPLL_DITHEN)); in oaktrail_crtc_hdmi_mode_set()
319 REG_WRITE(DPLL_UPDATE, 0x80000000); in oaktrail_crtc_hdmi_mode_set()
320 REG_WRITE(DPLL_CLK_ENABLE, 0x80050102); in oaktrail_crtc_hdmi_mode_set()
[all …]
H A Dgma_display.c91 REG_WRITE(map->stride, fb->pitches[0]); in gma_pipe_set_base()
115 REG_WRITE(map->cntr, dspcntr); in gma_pipe_set_base()
124 REG_WRITE(map->base, offset + start); in gma_pipe_set_base()
127 REG_WRITE(map->base, offset); in gma_pipe_set_base()
129 REG_WRITE(map->surf, start); in gma_pipe_set_base()
164 REG_WRITE(palreg + 4 * i, in gma_crtc_load_lut()
225 REG_WRITE(map->dpll, temp); in gma_crtc_dpms()
229 REG_WRITE(map->dpll, temp | DPLL_VCO_ENABLE); in gma_crtc_dpms()
233 REG_WRITE(map->dpll, temp | DPLL_VCO_ENABLE); in gma_crtc_dpms()
242 REG_WRITE(map->cntr, in gma_crtc_dpms()
[all …]
H A Dcdv_intel_display.c141 REG_WRITE(SB_ADDR, reg); in cdv_sb_read()
142 REG_WRITE(SB_PCKT, in cdv_sb_read()
176 REG_WRITE(SB_ADDR, reg); in cdv_sb_write()
177 REG_WRITE(SB_DATA, val); in cdv_sb_write()
178 REG_WRITE(SB_PCKT, in cdv_sb_write()
203 REG_WRITE(DPIO_CFG, 0); in cdv_sb_reset()
205 REG_WRITE(DPIO_CFG, DPIO_MODE_SELECT_0 | DPIO_CMN_RESET_N); in cdv_sb_reset()
228 REG_WRITE(dpll_reg, DPLL_SYNCLOCK_ENABLE | DPLL_VGA_MODE_DIS); in cdv_dpll_set_clock_cdv()
476 REG_WRITE(FW_BLC_SELF, (REG_READ(FW_BLC_SELF) & ~FW_BLC_SELF_EN)); in cdv_disable_sr()
484 REG_WRITE(OV_OVADD, 0/*dev_priv->ovl_offset*/); in cdv_disable_sr()
[all …]
H A Dpsb_intel_display.c215 REG_WRITE(PFIT_CONTROL, 0); in psb_intel_crtc_mode_set()
220 REG_WRITE(map->fp0, fp); in psb_intel_crtc_mode_set()
221 REG_WRITE(map->dpll, dpll & ~DPLL_VCO_ENABLE); in psb_intel_crtc_mode_set()
251 REG_WRITE(LVDS, lvds); in psb_intel_crtc_mode_set()
255 REG_WRITE(map->fp0, fp); in psb_intel_crtc_mode_set()
256 REG_WRITE(map->dpll, dpll); in psb_intel_crtc_mode_set()
262 REG_WRITE(map->dpll, dpll); in psb_intel_crtc_mode_set()
268 REG_WRITE(map->htotal, (adjusted_mode->crtc_hdisplay - 1) | in psb_intel_crtc_mode_set()
270 REG_WRITE(map->hblank, (adjusted_mode->crtc_hblank_start - 1) | in psb_intel_crtc_mode_set()
272 REG_WRITE(map->hsync, (adjusted_mode->crtc_hsync_start - 1) | in psb_intel_crtc_mode_set()
[all …]
H A Dpsb_intel_lvds.c148 REG_WRITE(BLC_PWM_CTL, in psb_lvds_pwm_set_brightness()
192 REG_WRITE(BLC_PWM_CTL, in psb_intel_lvds_set_backlight()
221 REG_WRITE(PP_CONTROL, REG_READ(PP_CONTROL) | in psb_intel_lvds_set_power()
232 REG_WRITE(PP_CONTROL, REG_READ(PP_CONTROL) & in psb_intel_lvds_set_power()
309 REG_WRITE(BLC_PWM_CTL, lvds_priv->saveBLC_PWM_CTL); in psb_intel_lvds_restore()
310 REG_WRITE(PFIT_CONTROL, lvds_priv->savePFIT_CONTROL); in psb_intel_lvds_restore()
311 REG_WRITE(PFIT_PGM_RATIOS, lvds_priv->savePFIT_PGM_RATIOS); in psb_intel_lvds_restore()
312 REG_WRITE(LVDSPP_ON, lvds_priv->savePP_ON); in psb_intel_lvds_restore()
313 REG_WRITE(LVDSPP_OFF, lvds_priv->savePP_OFF); in psb_intel_lvds_restore()
315 REG_WRITE(PP_CYCLE, lvds_priv->savePP_CYCLE); in psb_intel_lvds_restore()
[all …]
H A Dcdv_intel_crt.c68 REG_WRITE(reg, temp); in cdv_intel_crt_dpms()
113 REG_WRITE(dpll_md_reg, in cdv_intel_crt_mode_set()
128 REG_WRITE(adpa_reg, adpa); in cdv_intel_crt_mode_set()
162 REG_WRITE(PORT_HOTPLUG_EN, hotplug_en); in cdv_intel_crt_detect_hotplug()
178 REG_WRITE(PORT_HOTPLUG_STAT, CRT_HOTPLUG_INT_STATUS); in cdv_intel_crt_detect_hotplug()
181 REG_WRITE(PORT_HOTPLUG_EN, orig); in cdv_intel_crt_detect_hotplug()
H A Doaktrail_lvds.c47 REG_WRITE(PP_CONTROL, REG_READ(PP_CONTROL) | in oaktrail_lvds_set_power()
58 REG_WRITE(PP_CONTROL, REG_READ(PP_CONTROL) & in oaktrail_lvds_set_power()
112 REG_WRITE(LVDS, lvds_port); in oaktrail_lvds_mode_set()
133 REG_WRITE(PFIT_CONTROL, 0); in oaktrail_lvds_mode_set()
139 REG_WRITE(PFIT_CONTROL, PFIT_ENABLE); in oaktrail_lvds_mode_set()
143 REG_WRITE(PFIT_CONTROL, PFIT_ENABLE | in oaktrail_lvds_mode_set()
146 REG_WRITE(PFIT_CONTROL, PFIT_ENABLE | in oaktrail_lvds_mode_set()
149 REG_WRITE(PFIT_CONTROL, PFIT_ENABLE); in oaktrail_lvds_mode_set()
151 REG_WRITE(PFIT_CONTROL, PFIT_ENABLE); in oaktrail_lvds_mode_set()
/linux/drivers/net/wireless/ath/ath9k/
H A Dar9003_wow.c44 REG_WRITE(ah, AR_CR, AR_CR_RXD); in ath9k_hw_set_powermode_wow_sleep()
62 REG_WRITE(ah, AR_RTC_KEEP_AWAKE, 0x2); in ath9k_hw_set_powermode_wow_sleep()
64 REG_WRITE(ah, AR_RTC_FORCE_WAKE(ah), AR_RTC_FORCE_WAKE_ON_INT); in ath9k_hw_set_powermode_wow_sleep()
92 REG_WRITE(ah, (AR_WOW_KA_DESC_WORD2 + i * 4), ctl[i]); in ath9k_wow_create_keep_alive_pattern()
111 REG_WRITE(ah, (AR_WOW_KA_DESC_WORD2 + (12 * 4)), 0); in ath9k_wow_create_keep_alive_pattern()
118 REG_WRITE(ah, (wow_ka_data_word0 + i*4), data_word[i]); in ath9k_wow_create_keep_alive_pattern()
139 REG_WRITE(ah, (AR_WOW_TB_PATTERN(pattern_count) + i), in ath9k_hw_wow_apply_pattern()
146 REG_WRITE(ah, (AR_WOW_TB_MASK(pattern_count) + i), mask_val); in ath9k_hw_wow_apply_pattern()
235 REG_WRITE(ah, AR_WOW_PATTERN, in ath9k_hw_wow_wakeup()
237 REG_WRITE(ah, AR_MAC_PCU_WOW4, in ath9k_hw_wow_wakeup()
[all …]
H A Dar5008_phy.c98 REG_WRITE(ah, INI_RA(array, r, 0), data[r]); in ar5008_write_bank6()
236 REG_WRITE(ah, AR_PHY_CCK_TX_CTRL, in ar5008_hw_set_channel()
239 REG_WRITE(ah, AR_PHY_CCK_TX_CTRL, in ar5008_hw_set_channel()
268 REG_WRITE(ah, AR_PHY(0x37), reg32); in ar5008_hw_set_channel()
312 REG_WRITE(ah, pilot_mask_reg[i], pilot_mask); in ar5008_hw_cmn_spur_mitigate()
313 REG_WRITE(ah, chan_mask_reg[i], chan_mask); in ar5008_hw_cmn_spur_mitigate()
345 REG_WRITE(ah, AR_PHY_BIN_MASK_1, tmp_mask); in ar5008_hw_cmn_spur_mitigate()
346 REG_WRITE(ah, AR_PHY_VIT_MASK2_M_46_61, tmp_mask); in ar5008_hw_cmn_spur_mitigate()
356 REG_WRITE(ah, AR_PHY_BIN_MASK_2, tmp_mask); in ar5008_hw_cmn_spur_mitigate()
357 REG_WRITE(ah, AR_PHY_MASK2_M_31_45, tmp_mask); in ar5008_hw_cmn_spur_mitigate()
[all …]
H A Dhw.c118 REG_WRITE(ah, INI_RA(array, r, 0), in ath9k_hw_write_array()
331 REG_WRITE(ah, AR_PCIE_SERDES, 0x9248fc00); in ath9k_hw_disablepcie()
332 REG_WRITE(ah, AR_PCIE_SERDES, 0x24924924); in ath9k_hw_disablepcie()
333 REG_WRITE(ah, AR_PCIE_SERDES, 0x28000029); in ath9k_hw_disablepcie()
334 REG_WRITE(ah, AR_PCIE_SERDES, 0x57160824); in ath9k_hw_disablepcie()
335 REG_WRITE(ah, AR_PCIE_SERDES, 0x25980579); in ath9k_hw_disablepcie()
336 REG_WRITE(ah, AR_PCIE_SERDES, 0x00000000); in ath9k_hw_disablepcie()
337 REG_WRITE(ah, AR_PCIE_SERDES, 0x1aaabe40); in ath9k_hw_disablepcie()
338 REG_WRITE(ah, AR_PCIE_SERDES, 0xbe105554); in ath9k_hw_disablepcie()
339 REG_WRITE(ah, AR_PCIE_SERDES, 0x000e1007); in ath9k_hw_disablepcie()
[all …]
H A Dar9002_phy.c101 REG_WRITE(ah, AR_PHY_CCK_TX_CTRL, in ar9002_hw_set_channel()
104 REG_WRITE(ah, AR_PHY_CCK_TX_CTRL, in ar9002_hw_set_channel()
153 REG_WRITE(ah, AR_PHY_SYNTH_CONTROL, reg32); in ar9002_hw_set_channel()
233 REG_WRITE(ah, AR_PHY_TIMING_CTRL4(0), newVal); in ar9002_hw_spur_mitigate()
240 REG_WRITE(ah, AR_PHY_SPUR_REG, newVal); in ar9002_hw_spur_mitigate()
270 REG_WRITE(ah, AR_PHY_TIMING11, newVal); in ar9002_hw_spur_mitigate()
273 REG_WRITE(ah, AR_PHY_SFCORR_EXT, newVal); in ar9002_hw_spur_mitigate()
411 REG_WRITE(ah, AR_PHY_MULTICHAIN_GAIN_CTL, regval); in ar9002_hw_antdiv_comb_conf_set()
430 REG_WRITE(ah, AR_BT_COEX_MODE2, btcoex->bt_coex_mode2); in ar9002_hw_set_bt_ant_diversity()
432 REG_WRITE(ah, AR_PHY_SWITCH_COM, ATH_BT_COEX_ANT_DIV_SWITCH_COM); in ar9002_hw_set_bt_ant_diversity()
[all …]
H A Dmac.c32 REG_WRITE(ah, AR_IMR_S0, in ath9k_hw_set_txq_interrupts()
35 REG_WRITE(ah, AR_IMR_S1, in ath9k_hw_set_txq_interrupts()
41 REG_WRITE(ah, AR_IMR_S2, ah->imrs2_reg); in ath9k_hw_set_txq_interrupts()
54 REG_WRITE(ah, AR_QTXDP(q), txdp); in ath9k_hw_puttxbuf()
61 REG_WRITE(ah, AR_Q_TXE, 1 << q); in ath9k_hw_txstart()
123 REG_WRITE(ah, AR_TXCFG, in ath9k_hw_updatetxtriglevel()
146 REG_WRITE(ah, AR_Q_TXD, AR_Q_TXD_M); in ath9k_hw_abort_tx_dma()
166 REG_WRITE(ah, AR_Q_TXD, 0); in ath9k_hw_abort_tx_dma()
177 REG_WRITE(ah, AR_Q_TXD, 1 << q); in ath9k_hw_stop_dma_queue()
187 REG_WRITE(ah, AR_Q_TXD, 0); in ath9k_hw_stop_dma_queue()
[all …]
H A Dani.c135 REG_WRITE(ah, AR_PHY_ERR_1, 0); in ath9k_ani_restart()
136 REG_WRITE(ah, AR_PHY_ERR_2, 0); in ath9k_ani_restart()
137 REG_WRITE(ah, AR_PHY_ERR_MASK_1, AR_PHY_ERR_OFDM_TIMING); in ath9k_ani_restart()
138 REG_WRITE(ah, AR_PHY_ERR_MASK_2, AR_PHY_ERR_CCK_TIMING); in ath9k_ani_restart()
451 REG_WRITE(ah, AR_FILT_OFDM, 0); in ath9k_enable_mib_counters()
452 REG_WRITE(ah, AR_FILT_CCK, 0); in ath9k_enable_mib_counters()
453 REG_WRITE(ah, AR_MIBC, in ath9k_enable_mib_counters()
456 REG_WRITE(ah, AR_PHY_ERR_MASK_1, AR_PHY_ERR_OFDM_TIMING); in ath9k_enable_mib_counters()
457 REG_WRITE(ah, AR_PHY_ERR_MASK_2, AR_PHY_ERR_CCK_TIMING); in ath9k_enable_mib_counters()
469 REG_WRITE(ah, AR_MIBC, AR_MIBC_FMC); in ath9k_hw_disable_mib_counters()
[all …]
H A Dar9003_phy.c206 REG_WRITE(ah, AR_PHY_SYNTH_CONTROL, reg32); in ar9003_hw_set_channel()
215 REG_WRITE(ah, AR_PHY_65NM_CH0_SYNTH7, reg32); in ar9003_hw_set_channel()
221 REG_WRITE(ah, AR_PHY_65NM_CH0_SYNTH7, reg32); in ar9003_hw_set_channel()
639 REG_WRITE(ah, AR_PHY_GEN_CTRL, phymode); in ar9003_hw_set_channel_regs()
645 REG_WRITE(ah, AR_GTXTO, 25 << AR_GTXTO_TIMEOUT_LIMIT_S); in ar9003_hw_set_channel_regs()
647 REG_WRITE(ah, AR_CST, 0xF << AR_CST_TIMEOUT_LIMIT_S); in ar9003_hw_set_channel_regs()
663 REG_WRITE(ah, AR_PHY_ACTIVE, AR_PHY_ACTIVE_EN); in ar9003_hw_init_bb()
673 REG_WRITE(ah, AR_PHY_RX_CHAINMASK, rx); in ar9003_hw_set_chain_masks()
674 REG_WRITE(ah, AR_PHY_CAL_CHAINMASK, rx); in ar9003_hw_set_chain_masks()
679 REG_WRITE(ah, AR_SELFGEN_MASK, tx); in ar9003_hw_set_chain_masks()
[all …]
H A Dar9003_rtt.c40 REG_WRITE(ah, AR_PHY_RTT_CTRL, 1); in ar9003_hw_rtt_enable()
45 REG_WRITE(ah, AR_PHY_RTT_CTRL, 0); in ar9003_hw_rtt_disable()
78 REG_WRITE(ah, AR_PHY_RTT_TABLE_SW_INTF_1_B(chain), val); in ar9003_hw_rtt_load_hist_entry()
83 REG_WRITE(ah, AR_PHY_RTT_TABLE_SW_INTF_B(chain), val); in ar9003_hw_rtt_load_hist_entry()
87 REG_WRITE(ah, AR_PHY_RTT_TABLE_SW_INTF_B(chain), val); in ar9003_hw_rtt_load_hist_entry()
96 REG_WRITE(ah, AR_PHY_RTT_TABLE_SW_INTF_B(chain), val); in ar9003_hw_rtt_load_hist_entry()
150 REG_WRITE(ah, AR_PHY_RTT_TABLE_SW_INTF_B(chain), val); in ar9003_hw_rtt_fill_hist_entry()
154 REG_WRITE(ah, AR_PHY_RTT_TABLE_SW_INTF_B(chain), val); in ar9003_hw_rtt_fill_hist_entry()
H A Dar9002_calib.c61 REG_WRITE(ah, AR_PHY_CALMODE, AR_PHY_CALMODE_IQ); in ar9002_hw_setup_calibration()
66 REG_WRITE(ah, AR_PHY_CALMODE, AR_PHY_CALMODE_ADC_GAIN); in ar9002_hw_setup_calibration()
70 REG_WRITE(ah, AR_PHY_CALMODE, AR_PHY_CALMODE_ADC_DC_PER); in ar9002_hw_setup_calibration()
311 REG_WRITE(ah, AR_PHY_NEW_ADC_DC_GAIN_CORR(i), val); in ar9002_hw_adc_gaincal_calibrate()
318 REG_WRITE(ah, AR_PHY_NEW_ADC_DC_GAIN_CORR(0), in ar9002_hw_adc_gaincal_calibrate()
366 REG_WRITE(ah, AR_PHY_NEW_ADC_DC_GAIN_CORR(i), val); in ar9002_hw_adc_dccal_calibrate()
372 REG_WRITE(ah, AR_PHY_NEW_ADC_DC_GAIN_CORR(0), in ar9002_hw_adc_dccal_calibrate()
494 REG_WRITE(ah, AR9285_AN_TOP2, 0xca0358a0); in ar9271_hw_pa_cal()
502 REG_WRITE(ah, AR9285_AN_RF2G6, regVal); in ar9271_hw_pa_cal()
509 REG_WRITE(ah, AR9285_AN_RF2G6, regVal); in ar9271_hw_pa_cal()
[all …]
H A Deeprom_9287.c323 REG_WRITE(ah, 0xa270, tmpVal); in ar9287_eeprom_olpc_set_pdadcs()
330 REG_WRITE(ah, 0xb270, tmpVal); in ar9287_eeprom_olpc_set_pdadcs()
339 REG_WRITE(ah, 0xa398, tmpVal); in ar9287_eeprom_olpc_set_pdadcs()
349 REG_WRITE(ah, 0xb398, tmpVal); in ar9287_eeprom_olpc_set_pdadcs()
454 REG_WRITE(ah, in ath9k_hw_set_ar9287_power_cal_table()
482 REG_WRITE(ah, regOffset, reg32); in ath9k_hw_set_ar9287_power_cal_table()
749 REG_WRITE(ah, AR_PHY_POWER_TX_RATE1, in ath9k_hw_ar9287_set_txpower()
755 REG_WRITE(ah, AR_PHY_POWER_TX_RATE2, in ath9k_hw_ar9287_set_txpower()
763 REG_WRITE(ah, AR_PHY_POWER_TX_RATE3, in ath9k_hw_ar9287_set_txpower()
768 REG_WRITE(ah, AR_PHY_POWER_TX_RATE4, in ath9k_hw_ar9287_set_txpower()
[all …]
H A Dar9003_calib.c53 REG_WRITE(ah, AR_PHY_CALMODE, AR_PHY_CALMODE_IQ); in ar9003_hw_setup_calibration()
353 REG_WRITE(ah, AR_PHY_AGC_CONTROL(ah), in ar9003_hw_dynamic_osdac_selection()
390 REG_WRITE(ah, AR_PHY_AGC_CONTROL(ah), in ar9003_hw_dynamic_osdac_selection()
407 REG_WRITE(ah, AR_PHY_65NM_CH0_BB3, in ar9003_hw_dynamic_osdac_selection()
409 REG_WRITE(ah, AR_PHY_65NM_CH1_BB3, in ar9003_hw_dynamic_osdac_selection()
411 REG_WRITE(ah, AR_PHY_65NM_CH2_BB3, in ar9003_hw_dynamic_osdac_selection()
429 REG_WRITE(ah, AR_PHY_65NM_CH0_BB3, in ar9003_hw_dynamic_osdac_selection()
431 REG_WRITE(ah, AR_PHY_65NM_CH1_BB3, in ar9003_hw_dynamic_osdac_selection()
433 REG_WRITE(ah, AR_PHY_65NM_CH2_BB3, in ar9003_hw_dynamic_osdac_selection()
451 REG_WRITE(ah, AR_PHY_65NM_CH0_BB3, in ar9003_hw_dynamic_osdac_selection()
[all …]
/linux/drivers/gpu/drm/amd/display/dc/dccg/dcn20/
H A Ddcn20_dccg.c140 REG_WRITE(MICROSECOND_TIME_BASE_DIV, 0x00120264); in dccg2_init()
141 REG_WRITE(MILLISECOND_TIME_BASE_DIV, 0x001186a0); in dccg2_init()
142 REG_WRITE(DISPCLK_FREQ_CHANGE_CNTL, 0x0e01003c); in dccg2_init()
145 REG_WRITE(REFCLK_CNTL, 0); in dccg2_init()
154 REG_WRITE(REFCLK_CNTL, 0); in dccg2_refclk_setup()
169 REG_WRITE(DCCG_GATE_DISABLE_CNTL, 0); in dccg2_allow_clock_gating()
170 REG_WRITE(DCCG_GATE_DISABLE_CNTL2, 0); in dccg2_allow_clock_gating()
172 REG_WRITE(DCCG_GATE_DISABLE_CNTL, 0xFFFFFFFF); in dccg2_allow_clock_gating()
173 REG_WRITE(DCCG_GATE_DISABLE_CNTL2, 0xFFFFFFFF); in dccg2_allow_clock_gating()
/linux/drivers/gpu/drm/amd/display/dc/dce/
H A Ddce_abm.c70 REG_WRITE(MASTER_COMM_DATA_REG1, rampingBoundary); in dce_abm_set_pipe()
115 REG_WRITE(MASTER_COMM_DATA_REG1, frame_ramp); in dmcu_set_backlight_level()
131 REG_WRITE(BIOS_SCRATCH_2, s2); in dmcu_set_backlight_level()
142 REG_WRITE(DC_ABM1_HG_SAMPLE_RATE, 0x103); in dce_abm_init()
143 REG_WRITE(DC_ABM1_HG_SAMPLE_RATE, 0x101); in dce_abm_init()
144 REG_WRITE(DC_ABM1_LS_SAMPLE_RATE, 0x103); in dce_abm_init()
145 REG_WRITE(DC_ABM1_LS_SAMPLE_RATE, 0x101); in dce_abm_init()
146 REG_WRITE(BL1_PWM_BL_UPDATE_SAMPLE_RATE, 0x101); in dce_abm_init()
H A Ddce_transform.c158 REG_WRITE(SCL_SCALER_ENABLE, 0); in dce60_setup_scaling_configuration()
161 REG_WRITE(SCL_TAP_CONTROL, 0); in dce60_setup_scaling_configuration()
162 REG_WRITE(SCL_AUTOMATIC_MODE_CONTROL, 0); in dce60_setup_scaling_configuration()
163 REG_WRITE(SCL_F_SHARP_CONTROL, 0); in dce60_setup_scaling_configuration()
171 REG_WRITE(SCL_SCALER_ENABLE, 1); in dce60_setup_scaling_configuration()
262 REG_WRITE(DCFE_MEM_PWR_CTRL, power_ctl); in program_multi_taps_filter()
361 REG_WRITE(SCL_AUTOMATIC_MODE_CONTROL, 0); in program_scl_ratios_inits()
390 REG_WRITE(SCL_AUTOMATIC_MODE_CONTROL, 0); in dce60_program_scl_ratios_inits()
426 REG_WRITE(SCL_F_SHARP_CONTROL, 0); in dce_transform_set_scaler()
508 REG_WRITE(SCL_UPDATE, 0x00010000); in dce60_transform_set_scaler()
[all …]
H A Ddce_panel_cntl.c102 REG_WRITE(BL_PWM_CNTL, in dce_panel_cntl_hw_init()
104 REG_WRITE(BL_PWM_CNTL2, in dce_panel_cntl_hw_init()
106 REG_WRITE(BL_PWM_PERIOD_CNTL, in dce_panel_cntl_hw_init()
125 REG_WRITE(BL_PWM_CNTL, 0x8000FA00); in dce_panel_cntl_hw_init()
126 REG_WRITE(BL_PWM_PERIOD_CNTL, 0x000C0FA0); in dce_panel_cntl_hw_init()
133 REG_WRITE(BIOS_SCRATCH_2, value); in dce_panel_cntl_hw_init()
/linux/drivers/gpu/drm/amd/display/dc/hubbub/dcn401/
H A Ddcn401_hubbub.c503 REG_WRITE(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_B, reg); in hubbub401_init_watermarks()
506 REG_WRITE(DCHUBBUB_ARB_FRAC_URG_BW_FLIP_B, reg); in hubbub401_init_watermarks()
509 REG_WRITE(DCHUBBUB_ARB_FRAC_URG_BW_NOM_B, reg); in hubbub401_init_watermarks()
512 REG_WRITE(DCHUBBUB_ARB_FRAC_URG_BW_MALL_B, reg); in hubbub401_init_watermarks()
515 REG_WRITE(DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_B, reg); in hubbub401_init_watermarks()
518 REG_WRITE(DCHUBBUB_ARB_REFCYC_PER_META_TRIP_B, reg); in hubbub401_init_watermarks()
521 REG_WRITE(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_B, reg); in hubbub401_init_watermarks()
522 REG_WRITE(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK1_A, reg); in hubbub401_init_watermarks()
523 REG_WRITE(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK1_B, reg); in hubbub401_init_watermarks()
524 REG_WRITE(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK2_A, reg); in hubbub401_init_watermarks()
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