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Searched refs:REG_WRITE (Results 1 – 25 of 42) sorted by relevance

12

/linux/drivers/net/wireless/ath/
H A Dkey.c26 #define REG_WRITE(_ah, _reg, _val) (common->ops->write)(_ah, _val, _reg) macro
57 REG_WRITE(ah, AR_KEYTABLE_KEY0(entry), 0); in ath_hw_keyreset()
58 REG_WRITE(ah, AR_KEYTABLE_KEY1(entry), 0); in ath_hw_keyreset()
59 REG_WRITE(ah, AR_KEYTABLE_KEY2(entry), 0); in ath_hw_keyreset()
60 REG_WRITE(ah, AR_KEYTABLE_KEY3(entry), 0); in ath_hw_keyreset()
61 REG_WRITE(ah, AR_KEYTABLE_KEY4(entry), 0); in ath_hw_keyreset()
62 REG_WRITE(ah, AR_KEYTABLE_TYPE(entry), AR_KEYTABLE_TYPE_CLR); in ath_hw_keyreset()
63 REG_WRITE(ah, AR_KEYTABLE_MAC0(entry), 0); in ath_hw_keyreset()
64 REG_WRITE(ah, AR_KEYTABLE_MAC1(entry), 0); in ath_hw_keyreset()
69 REG_WRITE(ah, AR_KEYTABLE_KEY0(micentry), 0); in ath_hw_keyreset()
[all …]
H A Dhw.c24 #define REG_WRITE(_ah, _reg, _val) (common->ops->write)(_ah, _val, _reg) macro
123 REG_WRITE(ah, AR_STA_ID0, get_unaligned_le32(common->macaddr)); in ath_hw_setbssidmask()
126 REG_WRITE(ah, AR_STA_ID1, id1); in ath_hw_setbssidmask()
128 REG_WRITE(ah, AR_BSSMSKL, get_unaligned_le32(common->bssidmask)); in ath_hw_setbssidmask()
129 REG_WRITE(ah, AR_BSSMSKU, get_unaligned_le16(common->bssidmask + 4)); in ath_hw_setbssidmask()
148 REG_WRITE(ah, AR_MIBC, AR_MIBC_FMC); in ath_hw_cycle_counters_update()
157 REG_WRITE(ah, AR_CCCNT, 0); in ath_hw_cycle_counters_update()
158 REG_WRITE(ah, AR_RFCNT, 0); in ath_hw_cycle_counters_update()
159 REG_WRITE(ah, AR_RCCNT, 0); in ath_hw_cycle_counters_update()
160 REG_WRITE(ah, AR_TFCNT, 0); in ath_hw_cycle_counters_update()
[all …]
/linux/drivers/net/wireless/ath/ath9k/
H A Dar9003_wow.c44 REG_WRITE(ah, AR_CR, AR_CR_RXD); in ath9k_hw_set_powermode_wow_sleep()
62 REG_WRITE(ah, AR_RTC_KEEP_AWAKE, 0x2); in ath9k_hw_set_powermode_wow_sleep()
64 REG_WRITE(ah, AR_RTC_FORCE_WAKE(ah), AR_RTC_FORCE_WAKE_ON_INT); in ath9k_hw_set_powermode_wow_sleep()
92 REG_WRITE(ah, (AR_WOW_KA_DESC_WORD2 + i * 4), ctl[i]); in ath9k_wow_create_keep_alive_pattern()
111 REG_WRITE(ah, (AR_WOW_KA_DESC_WORD2 + (12 * 4)), 0); in ath9k_wow_create_keep_alive_pattern()
118 REG_WRITE(ah, (wow_ka_data_word0 + i*4), data_word[i]); in ath9k_wow_create_keep_alive_pattern()
139 REG_WRITE(ah, (AR_WOW_TB_PATTERN(pattern_count) + i), in ath9k_hw_wow_apply_pattern()
146 REG_WRITE(ah, (AR_WOW_TB_MASK(pattern_count) + i), mask_val); in ath9k_hw_wow_apply_pattern()
235 REG_WRITE(ah, AR_WOW_PATTERN, in ath9k_hw_wow_wakeup()
237 REG_WRITE(ah, AR_MAC_PCU_WOW4, in ath9k_hw_wow_wakeup()
[all …]
H A Dar5008_phy.c98 REG_WRITE(ah, INI_RA(array, r, 0), data[r]); in ar5008_write_bank6()
236 REG_WRITE(ah, AR_PHY_CCK_TX_CTRL, in ar5008_hw_set_channel()
239 REG_WRITE(ah, AR_PHY_CCK_TX_CTRL, in ar5008_hw_set_channel()
268 REG_WRITE(ah, AR_PHY(0x37), reg32); in ar5008_hw_set_channel()
312 REG_WRITE(ah, pilot_mask_reg[i], pilot_mask); in ar5008_hw_cmn_spur_mitigate()
313 REG_WRITE(ah, chan_mask_reg[i], chan_mask); in ar5008_hw_cmn_spur_mitigate()
345 REG_WRITE(ah, AR_PHY_BIN_MASK_1, tmp_mask); in ar5008_hw_cmn_spur_mitigate()
346 REG_WRITE(ah, AR_PHY_VIT_MASK2_M_46_61, tmp_mask); in ar5008_hw_cmn_spur_mitigate()
356 REG_WRITE(ah, AR_PHY_BIN_MASK_2, tmp_mask); in ar5008_hw_cmn_spur_mitigate()
357 REG_WRITE(ah, AR_PHY_MASK2_M_31_45, tmp_mask); in ar5008_hw_cmn_spur_mitigate()
[all …]
H A Dar9002_phy.c101 REG_WRITE(ah, AR_PHY_CCK_TX_CTRL, in ar9002_hw_set_channel()
104 REG_WRITE(ah, AR_PHY_CCK_TX_CTRL, in ar9002_hw_set_channel()
153 REG_WRITE(ah, AR_PHY_SYNTH_CONTROL, reg32); in ar9002_hw_set_channel()
233 REG_WRITE(ah, AR_PHY_TIMING_CTRL4(0), newVal); in ar9002_hw_spur_mitigate()
240 REG_WRITE(ah, AR_PHY_SPUR_REG, newVal); in ar9002_hw_spur_mitigate()
270 REG_WRITE(ah, AR_PHY_TIMING11, newVal); in ar9002_hw_spur_mitigate()
273 REG_WRITE(ah, AR_PHY_SFCORR_EXT, newVal); in ar9002_hw_spur_mitigate()
411 REG_WRITE(ah, AR_PHY_MULTICHAIN_GAIN_CTL, regval); in ar9002_hw_antdiv_comb_conf_set()
430 REG_WRITE(ah, AR_BT_COEX_MODE2, btcoex->bt_coex_mode2); in ar9002_hw_set_bt_ant_diversity()
432 REG_WRITE(ah, AR_PHY_SWITCH_COM, ATH_BT_COEX_ANT_DIV_SWITCH_COM); in ar9002_hw_set_bt_ant_diversity()
[all …]
H A Dmac.c32 REG_WRITE(ah, AR_IMR_S0, in ath9k_hw_set_txq_interrupts()
35 REG_WRITE(ah, AR_IMR_S1, in ath9k_hw_set_txq_interrupts()
41 REG_WRITE(ah, AR_IMR_S2, ah->imrs2_reg); in ath9k_hw_set_txq_interrupts()
54 REG_WRITE(ah, AR_QTXDP(q), txdp); in ath9k_hw_puttxbuf()
61 REG_WRITE(ah, AR_Q_TXE, 1 << q); in ath9k_hw_txstart()
123 REG_WRITE(ah, AR_TXCFG, in ath9k_hw_updatetxtriglevel()
146 REG_WRITE(ah, AR_Q_TXD, AR_Q_TXD_M); in ath9k_hw_abort_tx_dma()
166 REG_WRITE(ah, AR_Q_TXD, 0); in ath9k_hw_abort_tx_dma()
177 REG_WRITE(ah, AR_Q_TXD, 1 << q); in ath9k_hw_stop_dma_queue()
187 REG_WRITE(ah, AR_Q_TXD, 0); in ath9k_hw_stop_dma_queue()
[all …]
H A Dani.c135 REG_WRITE(ah, AR_PHY_ERR_1, 0); in ath9k_ani_restart()
136 REG_WRITE(ah, AR_PHY_ERR_2, 0); in ath9k_ani_restart()
137 REG_WRITE(ah, AR_PHY_ERR_MASK_1, AR_PHY_ERR_OFDM_TIMING); in ath9k_ani_restart()
138 REG_WRITE(ah, AR_PHY_ERR_MASK_2, AR_PHY_ERR_CCK_TIMING); in ath9k_ani_restart()
451 REG_WRITE(ah, AR_FILT_OFDM, 0); in ath9k_enable_mib_counters()
452 REG_WRITE(ah, AR_FILT_CCK, 0); in ath9k_enable_mib_counters()
453 REG_WRITE(ah, AR_MIBC, in ath9k_enable_mib_counters()
456 REG_WRITE(ah, AR_PHY_ERR_MASK_1, AR_PHY_ERR_OFDM_TIMING); in ath9k_enable_mib_counters()
457 REG_WRITE(ah, AR_PHY_ERR_MASK_2, AR_PHY_ERR_CCK_TIMING); in ath9k_enable_mib_counters()
469 REG_WRITE(ah, AR_MIBC, AR_MIBC_FMC); in ath9k_hw_disable_mib_counters()
[all …]
H A Dar9003_rtt.c40 REG_WRITE(ah, AR_PHY_RTT_CTRL, 1); in ar9003_hw_rtt_enable()
45 REG_WRITE(ah, AR_PHY_RTT_CTRL, 0); in ar9003_hw_rtt_disable()
78 REG_WRITE(ah, AR_PHY_RTT_TABLE_SW_INTF_1_B(chain), val); in ar9003_hw_rtt_load_hist_entry()
83 REG_WRITE(ah, AR_PHY_RTT_TABLE_SW_INTF_B(chain), val); in ar9003_hw_rtt_load_hist_entry()
87 REG_WRITE(ah, AR_PHY_RTT_TABLE_SW_INTF_B(chain), val); in ar9003_hw_rtt_load_hist_entry()
96 REG_WRITE(ah, AR_PHY_RTT_TABLE_SW_INTF_B(chain), val); in ar9003_hw_rtt_load_hist_entry()
150 REG_WRITE(ah, AR_PHY_RTT_TABLE_SW_INTF_B(chain), val); in ar9003_hw_rtt_fill_hist_entry()
154 REG_WRITE(ah, AR_PHY_RTT_TABLE_SW_INTF_B(chain), val); in ar9003_hw_rtt_fill_hist_entry()
H A Dar9002_calib.c61 REG_WRITE(ah, AR_PHY_CALMODE, AR_PHY_CALMODE_IQ); in ar9002_hw_setup_calibration()
66 REG_WRITE(ah, AR_PHY_CALMODE, AR_PHY_CALMODE_ADC_GAIN); in ar9002_hw_setup_calibration()
70 REG_WRITE(ah, AR_PHY_CALMODE, AR_PHY_CALMODE_ADC_DC_PER); in ar9002_hw_setup_calibration()
311 REG_WRITE(ah, AR_PHY_NEW_ADC_DC_GAIN_CORR(i), val); in ar9002_hw_adc_gaincal_calibrate()
318 REG_WRITE(ah, AR_PHY_NEW_ADC_DC_GAIN_CORR(0), in ar9002_hw_adc_gaincal_calibrate()
366 REG_WRITE(ah, AR_PHY_NEW_ADC_DC_GAIN_CORR(i), val); in ar9002_hw_adc_dccal_calibrate()
372 REG_WRITE(ah, AR_PHY_NEW_ADC_DC_GAIN_CORR(0), in ar9002_hw_adc_dccal_calibrate()
494 REG_WRITE(ah, AR9285_AN_TOP2, 0xca0358a0); in ar9271_hw_pa_cal()
502 REG_WRITE(ah, AR9285_AN_RF2G6, regVal); in ar9271_hw_pa_cal()
509 REG_WRITE(ah, AR9285_AN_RF2G6, regVal); in ar9271_hw_pa_cal()
[all …]
H A Deeprom_9287.c323 REG_WRITE(ah, 0xa270, tmpVal); in ar9287_eeprom_olpc_set_pdadcs()
330 REG_WRITE(ah, 0xb270, tmpVal); in ar9287_eeprom_olpc_set_pdadcs()
339 REG_WRITE(ah, 0xa398, tmpVal); in ar9287_eeprom_olpc_set_pdadcs()
349 REG_WRITE(ah, 0xb398, tmpVal); in ar9287_eeprom_olpc_set_pdadcs()
454 REG_WRITE(ah, in ath9k_hw_set_ar9287_power_cal_table()
482 REG_WRITE(ah, regOffset, reg32); in ath9k_hw_set_ar9287_power_cal_table()
749 REG_WRITE(ah, AR_PHY_POWER_TX_RATE1, in ath9k_hw_ar9287_set_txpower()
755 REG_WRITE(ah, AR_PHY_POWER_TX_RATE2, in ath9k_hw_ar9287_set_txpower()
763 REG_WRITE(ah, AR_PHY_POWER_TX_RATE3, in ath9k_hw_ar9287_set_txpower()
768 REG_WRITE(ah, AR_PHY_POWER_TX_RATE4, in ath9k_hw_ar9287_set_txpower()
[all …]
H A Dar9003_calib.c53 REG_WRITE(ah, AR_PHY_CALMODE, AR_PHY_CALMODE_IQ); in ar9003_hw_setup_calibration()
353 REG_WRITE(ah, AR_PHY_AGC_CONTROL(ah), in ar9003_hw_dynamic_osdac_selection()
390 REG_WRITE(ah, AR_PHY_AGC_CONTROL(ah), in ar9003_hw_dynamic_osdac_selection()
407 REG_WRITE(ah, AR_PHY_65NM_CH0_BB3, in ar9003_hw_dynamic_osdac_selection()
409 REG_WRITE(ah, AR_PHY_65NM_CH1_BB3, in ar9003_hw_dynamic_osdac_selection()
411 REG_WRITE(ah, AR_PHY_65NM_CH2_BB3, in ar9003_hw_dynamic_osdac_selection()
429 REG_WRITE(ah, AR_PHY_65NM_CH0_BB3, in ar9003_hw_dynamic_osdac_selection()
431 REG_WRITE(ah, AR_PHY_65NM_CH1_BB3, in ar9003_hw_dynamic_osdac_selection()
433 REG_WRITE(ah, AR_PHY_65NM_CH2_BB3, in ar9003_hw_dynamic_osdac_selection()
451 REG_WRITE(ah, AR_PHY_65NM_CH0_BB3, in ar9003_hw_dynamic_osdac_selection()
[all …]
H A Deeprom_def.c479 REG_WRITE(ah, AR_PHY_SWITCH_COM, antCtrlCommon & 0xffff); in ath9k_hw_def_set_board_values()
492 REG_WRITE(ah, AR_PHY_SWITCH_CHAIN_0 + regChainOffset, in ath9k_hw_def_set_board_values()
495 REG_WRITE(ah, AR_PHY_TIMING_CTRL4(0) + regChainOffset, in ath9k_hw_def_set_board_values()
567 REG_WRITE(ah, AR_PHY_RF_CTL4, in ath9k_hw_def_set_board_values()
873 REG_WRITE(ah, in ath9k_hw_set_def_power_cal_table()
880 REG_WRITE(ah, in ath9k_hw_set_def_power_cal_table()
896 REG_WRITE(ah, regOffset, reg32); in ath9k_hw_set_def_power_cal_table()
1194 REG_WRITE(ah, AR_PHY_POWER_TX_RATE1, in ath9k_hw_def_set_txpower()
1199 REG_WRITE(ah, AR_PHY_POWER_TX_RATE2, in ath9k_hw_def_set_txpower()
1208 REG_WRITE(ah, AR_PHY_POWER_TX_RATE3, in ath9k_hw_def_set_txpower()
[all …]
H A Deeprom_4k.c346 REG_WRITE(ah, AR_PHY_TPCRG5 + regChainOffset, in ath9k_hw_set_4k_power_cal_table()
361 REG_WRITE(ah, regOffset, reg32); in ath9k_hw_set_4k_power_cal_table()
620 REG_WRITE(ah, AR_PHY_POWER_TX_RATE1, in ath9k_hw_4k_set_txpower()
625 REG_WRITE(ah, AR_PHY_POWER_TX_RATE2, in ath9k_hw_4k_set_txpower()
632 REG_WRITE(ah, AR_PHY_POWER_TX_RATE3, in ath9k_hw_4k_set_txpower()
637 REG_WRITE(ah, AR_PHY_POWER_TX_RATE4, in ath9k_hw_4k_set_txpower()
644 REG_WRITE(ah, AR_PHY_POWER_TX_RATE5, in ath9k_hw_4k_set_txpower()
649 REG_WRITE(ah, AR_PHY_POWER_TX_RATE6, in ath9k_hw_4k_set_txpower()
657 REG_WRITE(ah, AR_PHY_POWER_TX_RATE7, in ath9k_hw_4k_set_txpower()
666 REG_WRITE(ah, AR_PHY_POWER_TX_RATE8, in ath9k_hw_4k_set_txpower()
[all …]
/linux/drivers/gpu/drm/gma500/
H A Dgma_display.c91 REG_WRITE(map->stride, fb->pitches[0]); in gma_pipe_set_base()
115 REG_WRITE(map->cntr, dspcntr); in gma_pipe_set_base()
124 REG_WRITE(map->base, offset + start); in gma_pipe_set_base()
127 REG_WRITE(map->base, offset); in gma_pipe_set_base()
129 REG_WRITE(map->surf, start); in gma_pipe_set_base()
164 REG_WRITE(palreg + 4 * i, in gma_crtc_load_lut()
225 REG_WRITE(map->dpll, temp); in gma_crtc_dpms()
229 REG_WRITE(map->dpll, temp | DPLL_VCO_ENABLE); in gma_crtc_dpms()
233 REG_WRITE(map->dpll, temp | DPLL_VCO_ENABLE); in gma_crtc_dpms()
242 REG_WRITE(map->cntr, in gma_crtc_dpms()
[all …]
H A Dcdv_intel_display.c141 REG_WRITE(SB_ADDR, reg); in cdv_sb_read()
142 REG_WRITE(SB_PCKT, in cdv_sb_read()
176 REG_WRITE(SB_ADDR, reg); in cdv_sb_write()
177 REG_WRITE(SB_DATA, val); in cdv_sb_write()
178 REG_WRITE(SB_PCKT, in cdv_sb_write()
203 REG_WRITE(DPIO_CFG, 0); in cdv_sb_reset()
205 REG_WRITE(DPIO_CFG, DPIO_MODE_SELECT_0 | DPIO_CMN_RESET_N); in cdv_sb_reset()
228 REG_WRITE(dpll_reg, DPLL_SYNCLOCK_ENABLE | DPLL_VGA_MODE_DIS); in cdv_dpll_set_clock_cdv()
476 REG_WRITE(FW_BLC_SELF, (REG_READ(FW_BLC_SELF) & ~FW_BLC_SELF_EN)); in cdv_disable_sr()
484 REG_WRITE(OV_OVADD, 0/*dev_priv->ovl_offset*/); in cdv_disable_sr()
[all …]
H A Dpsb_intel_display.c215 REG_WRITE(PFIT_CONTROL, 0); in psb_intel_crtc_mode_set()
220 REG_WRITE(map->fp0, fp); in psb_intel_crtc_mode_set()
221 REG_WRITE(map->dpll, dpll & ~DPLL_VCO_ENABLE); in psb_intel_crtc_mode_set()
251 REG_WRITE(LVDS, lvds); in psb_intel_crtc_mode_set()
255 REG_WRITE(map->fp0, fp); in psb_intel_crtc_mode_set()
256 REG_WRITE(map->dpll, dpll); in psb_intel_crtc_mode_set()
262 REG_WRITE(map->dpll, dpll); in psb_intel_crtc_mode_set()
268 REG_WRITE(map->htotal, (adjusted_mode->crtc_hdisplay - 1) | in psb_intel_crtc_mode_set()
270 REG_WRITE(map->hblank, (adjusted_mode->crtc_hblank_start - 1) | in psb_intel_crtc_mode_set()
272 REG_WRITE(map->hsync, (adjusted_mode->crtc_hsync_start - 1) | in psb_intel_crtc_mode_set()
[all …]
/linux/drivers/gpu/drm/amd/display/dc/dccg/dcn20/
H A Ddcn20_dccg.c140 REG_WRITE(MICROSECOND_TIME_BASE_DIV, 0x00120264); in dccg2_init()
141 REG_WRITE(MILLISECOND_TIME_BASE_DIV, 0x001186a0); in dccg2_init()
142 REG_WRITE(DISPCLK_FREQ_CHANGE_CNTL, 0x0e01003c); in dccg2_init()
145 REG_WRITE(REFCLK_CNTL, 0); in dccg2_init()
154 REG_WRITE(REFCLK_CNTL, 0); in dccg2_refclk_setup()
169 REG_WRITE(DCCG_GATE_DISABLE_CNTL, 0); in dccg2_allow_clock_gating()
170 REG_WRITE(DCCG_GATE_DISABLE_CNTL2, 0); in dccg2_allow_clock_gating()
172 REG_WRITE(DCCG_GATE_DISABLE_CNTL, 0xFFFFFFFF); in dccg2_allow_clock_gating()
173 REG_WRITE(DCCG_GATE_DISABLE_CNTL2, 0xFFFFFFFF); in dccg2_allow_clock_gating()
/linux/drivers/gpu/drm/amd/display/dc/dccg/dcn21/
H A Ddcn21_dccg.c122 REG_WRITE(MICROSECOND_TIME_BASE_DIV, 0x00120230); in dccg21_init()
123 REG_WRITE(MILLISECOND_TIME_BASE_DIV, 0x0010bb80); in dccg21_init()
124 REG_WRITE(DISPCLK_FREQ_CHANGE_CNTL, 0x0e01003c); in dccg21_init()
127 REG_WRITE(REFCLK_CNTL, 0); in dccg21_init()
/linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn30/
H A Ddcn30m_clk_mgr_smu_msg.c84 REG_WRITE(DAL_RESP_REG, 0); in dcn30m_smu_send_msg_with_param()
87 REG_WRITE(DAL_ARG_REG, param_in); in dcn30m_smu_send_msg_with_param()
90 REG_WRITE(DAL_MSG_REG, msg_id); in dcn30m_smu_send_msg_with_param()
/linux/drivers/gpu/drm/amd/display/dc/dcn301/
H A Ddcn301_panel_cntl.c110 REG_WRITE(BL_PWM_CNTL, in dcn301_panel_cntl_hw_init()
112 REG_WRITE(BL_PWM_CNTL2, in dcn301_panel_cntl_hw_init()
114 REG_WRITE(BL_PWM_PERIOD_CNTL, in dcn301_panel_cntl_hw_init()
123 REG_WRITE(BL_PWM_CNTL, 0xC000FA00); in dcn301_panel_cntl_hw_init()
124 REG_WRITE(BL_PWM_PERIOD_CNTL, 0x000C0FA0); in dcn301_panel_cntl_hw_init()
/linux/drivers/net/wireless/st/cw1200/
H A Dfwio.c80 #define REG_WRITE(reg, val) \ in cw1200_load_firmware_cw1200() macro
132 REG_WRITE(ST90TDS_SRAM_BASE_ADDR_REG_ID, 0xFFF20000); in cw1200_load_firmware_cw1200()
133 REG_WRITE(ST90TDS_AHB_DPORT_REG_ID, 0xEAFFFFFE); in cw1200_load_firmware_cw1200()
138 REG_WRITE(ST90TDS_CONFIG_REG_ID, val32); in cw1200_load_firmware_cw1200()
142 REG_WRITE(ST90TDS_CONFIG_REG_ID, val32); in cw1200_load_firmware_cw1200()
260 #undef REG_WRITE in cw1200_load_firmware_cw1200()
/linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn314/
H A Ddcn314_smu.c135 REG_WRITE(MP1_SMN_C2PMSG_91, VBIOSSMC_Status_BUSY); in dcn314_smu_send_msg_with_param()
138 REG_WRITE(MP1_SMN_C2PMSG_83, param); in dcn314_smu_send_msg_with_param()
141 REG_WRITE(MP1_SMN_C2PMSG_67, msg_id); in dcn314_smu_send_msg_with_param()
154 REG_WRITE(MP1_SMN_C2PMSG_91, VBIOSSMC_Result_OK); in dcn314_smu_send_msg_with_param()
/linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/
H A Ddcn31_smu.c119 REG_WRITE(MP1_SMN_C2PMSG_91, VBIOSSMC_Status_BUSY); in dcn31_smu_send_msg_with_param()
122 REG_WRITE(MP1_SMN_C2PMSG_83, param); in dcn31_smu_send_msg_with_param()
125 REG_WRITE(MP1_SMN_C2PMSG_67, msg_id); in dcn31_smu_send_msg_with_param()
135 REG_WRITE(MP1_SMN_C2PMSG_91, VBIOSSMC_Result_OK); in dcn31_smu_send_msg_with_param()
/linux/drivers/gpu/drm/amd/display/dc/dce/
H A Ddce_stream_encoder.c120 REG_WRITE(AFMT_GENERIC_0, *content++); in dce110_update_generic_info_packet()
121 REG_WRITE(AFMT_GENERIC_1, *content++); in dce110_update_generic_info_packet()
122 REG_WRITE(AFMT_GENERIC_2, *content++); in dce110_update_generic_info_packet()
123 REG_WRITE(AFMT_GENERIC_3, *content++); in dce110_update_generic_info_packet()
124 REG_WRITE(AFMT_GENERIC_4, *content++); in dce110_update_generic_info_packet()
125 REG_WRITE(AFMT_GENERIC_5, *content++); in dce110_update_generic_info_packet()
126 REG_WRITE(AFMT_GENERIC_6, *content++); in dce110_update_generic_info_packet()
127 REG_WRITE(AFMT_GENERIC_7, *content); in dce110_update_generic_info_packet()
458 REG_WRITE(DP_MSA_MISC, misc1); /* MSA_MISC1 */ in dce110_stream_encoder_dp_set_stream_attribute()
514 REG_WRITE(DP_MSA_MISC, misc1); /* MSA_MISC1 */ in dce110_stream_encoder_dp_set_stream_attribute()
[all …]
/linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn301/
H A Ddcn301_smu.c114 REG_WRITE(MP1_SMN_C2PMSG_91, VBIOSSMC_Status_BUSY); in dcn301_smu_send_msg_with_param()
117 REG_WRITE(MP1_SMN_C2PMSG_83, param); in dcn301_smu_send_msg_with_param()
120 REG_WRITE(MP1_SMN_C2PMSG_67, msg_id); in dcn301_smu_send_msg_with_param()

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