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Searched refs:REG_UPDATE_2 (Results 1 – 25 of 42) sorted by relevance

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/linux/drivers/gpu/drm/amd/display/dc/dccg/dcn401/
H A Ddcn401_dccg.c230 REG_UPDATE_2(DTBCLK_P_CNTL, in dccg401_set_dtbclk_p_src()
239 REG_UPDATE_2(DTBCLK_P_CNTL, in dccg401_set_dtbclk_p_src()
248 REG_UPDATE_2(DTBCLK_P_CNTL, in dccg401_set_dtbclk_p_src()
257 REG_UPDATE_2(DTBCLK_P_CNTL, in dccg401_set_dtbclk_p_src()
280 REG_UPDATE_2(PHYASYMCLK_CLOCK_CNTL, in dccg401_set_physymclk()
287 REG_UPDATE_2(PHYASYMCLK_CLOCK_CNTL, in dccg401_set_physymclk()
297 REG_UPDATE_2(PHYBSYMCLK_CLOCK_CNTL, in dccg401_set_physymclk()
304 REG_UPDATE_2(PHYBSYMCLK_CLOCK_CNTL, in dccg401_set_physymclk()
314 REG_UPDATE_2(PHYCSYMCLK_CLOCK_CNTL, in dccg401_set_physymclk()
321 REG_UPDATE_2(PHYCSYMCLK_CLOCK_CNTL, in dccg401_set_physymclk()
[all …]
/linux/drivers/gpu/drm/amd/display/dc/dccg/dcn35/
H A Ddcn35_dccg.c182 REG_UPDATE_2(DCCG_GATE_DISABLE_CNTL3, in dccg35_set_symclk32_se_rcg()
187 REG_UPDATE_2(DCCG_GATE_DISABLE_CNTL3, in dccg35_set_symclk32_se_rcg()
192 REG_UPDATE_2(DCCG_GATE_DISABLE_CNTL3, in dccg35_set_symclk32_se_rcg()
197 REG_UPDATE_2(DCCG_GATE_DISABLE_CNTL3, in dccg35_set_symclk32_se_rcg()
219 REG_UPDATE_2(DCCG_GATE_DISABLE_CNTL3, in dccg35_set_symclk32_le_rcg()
224 REG_UPDATE_2(DCCG_GATE_DISABLE_CNTL3, in dccg35_set_symclk32_le_rcg()
436 REG_UPDATE_2(DCCG_GATE_DISABLE_CNTL5, in dccg35_set_dpstreamclk_rcg()
441 REG_UPDATE_2(DCCG_GATE_DISABLE_CNTL5, in dccg35_set_dpstreamclk_rcg()
446 REG_UPDATE_2(DCCG_GATE_DISABLE_CNTL5, in dccg35_set_dpstreamclk_rcg()
451 REG_UPDATE_2(DCCG_GATE_DISABLE_CNTL5, in dccg35_set_dpstreamclk_rcg()
[all …]
/linux/drivers/gpu/drm/amd/display/dc/dccg/dcn31/
H A Ddcn31_dccg.c125 REG_UPDATE_2(DCCG_GATE_DISABLE_CNTL3, in dccg31_enable_dpstreamclk()
135 REG_UPDATE_2(DCCG_GATE_DISABLE_CNTL3, in dccg31_disable_dpstreamclk()
187 REG_UPDATE_2(DCCG_GATE_DISABLE_CNTL3, in dccg31_enable_symclk32_se()
190 REG_UPDATE_2(SYMCLK32_SE_CNTL, in dccg31_enable_symclk32_se()
196 REG_UPDATE_2(DCCG_GATE_DISABLE_CNTL3, in dccg31_enable_symclk32_se()
199 REG_UPDATE_2(SYMCLK32_SE_CNTL, in dccg31_enable_symclk32_se()
205 REG_UPDATE_2(DCCG_GATE_DISABLE_CNTL3, in dccg31_enable_symclk32_se()
208 REG_UPDATE_2(SYMCLK32_SE_CNTL, in dccg31_enable_symclk32_se()
214 REG_UPDATE_2(DCCG_GATE_DISABLE_CNTL3, in dccg31_enable_symclk32_se()
217 REG_UPDATE_2(SYMCLK32_SE_CNTL, in dccg31_enable_symclk32_se()
[all …]
/linux/drivers/gpu/drm/amd/display/dc/dccg/dcn32/
H A Ddcn32_dccg.c124 REG_UPDATE_2(OTG_PIXEL_RATE_DIV, in dccg32_set_pixel_rate_div()
129 REG_UPDATE_2(OTG_PIXEL_RATE_DIV, in dccg32_set_pixel_rate_div()
134 REG_UPDATE_2(OTG_PIXEL_RATE_DIV, in dccg32_set_pixel_rate_div()
139 REG_UPDATE_2(OTG_PIXEL_RATE_DIV, in dccg32_set_pixel_rate_div()
166 REG_UPDATE_2(DTBCLK_P_CNTL, in dccg32_set_dtbclk_p_src()
175 REG_UPDATE_2(DTBCLK_P_CNTL, in dccg32_set_dtbclk_p_src()
184 REG_UPDATE_2(DTBCLK_P_CNTL, in dccg32_set_dtbclk_p_src()
193 REG_UPDATE_2(DTBCLK_P_CNTL, in dccg32_set_dtbclk_p_src()
240 REG_UPDATE_2(OTG_PIXEL_RATE_CNTL[params->otg_inst], in dccg32_set_dtbclk_dto()
291 REG_UPDATE_2(DPSTREAMCLK_CNTL, in dccg32_set_dpstreamclk()
[all …]
/linux/drivers/gpu/drm/amd/display/dc/dce/
H A Ddce_opp.c156 REG_UPDATE_2(FMT_BIT_DEPTH_CONTROL, in dce60_set_truncation()
163 REG_UPDATE_2(FMT_BIT_DEPTH_CONTROL, in dce60_set_truncation()
168 REG_UPDATE_2(FMT_BIT_DEPTH_CONTROL, in dce60_set_truncation()
177 REG_UPDATE_2(FMT_BIT_DEPTH_CONTROL, in dce60_set_truncation()
227 REG_UPDATE_2(FMT_CONTROL, in set_spatial_dither()
231 REG_UPDATE_2(FMT_CONTROL, in set_spatial_dither()
237 REG_UPDATE_2(FMT_CONTROL, in set_spatial_dither()
311 REG_UPDATE_2(FMT_BIT_DEPTH_CONTROL, in set_temporal_dither()
481 REG_UPDATE_2(FMT_CONTROL, in set_pixel_encoding()
486 REG_UPDATE_2(FMT_CONTROL, in set_pixel_encoding()
[all …]
H A Ddce_stream_encoder.c132 REG_UPDATE_2(AFMT_VBI_PACKET_CONTROL, in dce110_update_generic_info_packet()
438 REG_UPDATE_2( in dce110_stream_encoder_dp_set_stream_attribute()
576 REG_UPDATE_2(HDMI_CONTROL, in dce110_stream_encoder_hdmi_set_stream_attribute()
580 REG_UPDATE_2(HDMI_CONTROL, in dce110_stream_encoder_hdmi_set_stream_attribute()
587 REG_UPDATE_2(HDMI_CONTROL, in dce110_stream_encoder_hdmi_set_stream_attribute()
591 REG_UPDATE_2(HDMI_CONTROL, in dce110_stream_encoder_hdmi_set_stream_attribute()
597 REG_UPDATE_2(HDMI_CONTROL, in dce110_stream_encoder_hdmi_set_stream_attribute()
611 REG_UPDATE_2(HDMI_CONTROL, in dce110_stream_encoder_hdmi_set_stream_attribute()
623 REG_UPDATE_2(HDMI_CONTROL, in dce110_stream_encoder_hdmi_set_stream_attribute()
751 REG_UPDATE_2(HDMI_INFOFRAME_CONTROL0, in dce110_stream_encoder_update_hdmi_info_packets()
[all …]
H A Ddce_abm.c73 REG_UPDATE_2(MASTER_COMM_CMD_REG, in dce_abm_set_pipe()
167 REG_UPDATE_2(DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES, in dce_abm_init()
210 REG_UPDATE_2(MASTER_COMM_CMD_REG, in dce_abm_set_level()
H A Ddce_mem_input.c158 REG_UPDATE_2(DVMM_PTE_ARB_CONTROL, in dce_mi_program_pte_vm()
287 REG_UPDATE_2(DPG_PIPE_STUTTER_CONTROL2, in dce120_program_stutter_watermark()
291 REG_UPDATE_2(DPG_PIPE_STUTTER_CONTROL, in dce120_program_stutter_watermark()
328 REG_UPDATE_2(DPG_PIPE_STUTTER_CONTROL, in dce_mi_program_display_marks()
355 REG_UPDATE_2(DPG_PIPE_STUTTER_CONTROL, in dce60_mi_program_display_marks()
385 REG_UPDATE_2(DPG_PIPE_STUTTER_CONTROL, in dce112_mi_program_display_marks()
418 REG_UPDATE_2(DPG_PIPE_STUTTER_CONTROL, in dce120_mi_program_display_marks()
618 REG_UPDATE_2(GRPH_CONTROL, in program_grph_pixel_format()
H A Ddce_dmcu.c87 REG_UPDATE_2(DMCU_RAM_ACCESS_CTRL, in dce_dmcu_load_iram()
99 REG_UPDATE_2(DMCU_RAM_ACCESS_CTRL, in dce_dmcu_load_iram()
337 REG_UPDATE_2(DMCU_RAM_ACCESS_CTRL, in dcn10_get_dmcu_version()
352 REG_UPDATE_2(DMCU_RAM_ACCESS_CTRL, in dcn10_get_dmcu_version()
487 REG_UPDATE_2(DMCU_RAM_ACCESS_CTRL, in dcn10_dmcu_load_iram()
499 REG_UPDATE_2(DMCU_RAM_ACCESS_CTRL, in dcn10_dmcu_load_iram()
H A Ddce_link_encoder.c360 REG_UPDATE_2(DP_DPHY_PRBS_CNTL, in set_dp_phy_pattern_symbol_error()
380 REG_UPDATE_2(DP_DPHY_PRBS_CNTL, in set_dp_phy_pattern_prbs7()
697 REG_UPDATE_2(DP_SEC_CNTL1, in dce110_psr_program_secondary_packet()
1642 REG_UPDATE_2(DP_MSE_SAT0, in dce110_link_encoder_update_mst_stream_allocation_table()
1656 REG_UPDATE_2(DP_MSE_SAT0, in dce110_link_encoder_update_mst_stream_allocation_table()
1670 REG_UPDATE_2(DP_MSE_SAT1, in dce110_link_encoder_update_mst_stream_allocation_table()
1684 REG_UPDATE_2(DP_MSE_SAT1, in dce110_link_encoder_update_mst_stream_allocation_table()
/linux/drivers/gpu/drm/amd/display/dc/dccg/dcn314/
H A Ddcn314_dccg.c124 REG_UPDATE_2(OTG_PIXEL_RATE_DIV, in dccg314_set_pixel_rate_div()
129 REG_UPDATE_2(OTG_PIXEL_RATE_DIV, in dccg314_set_pixel_rate_div()
134 REG_UPDATE_2(OTG_PIXEL_RATE_DIV, in dccg314_set_pixel_rate_div()
139 REG_UPDATE_2(OTG_PIXEL_RATE_DIV, in dccg314_set_pixel_rate_div()
167 REG_UPDATE_2(DTBCLK_P_CNTL, in dccg314_set_dtbclk_p_src()
176 REG_UPDATE_2(DTBCLK_P_CNTL, in dccg314_set_dtbclk_p_src()
185 REG_UPDATE_2(DTBCLK_P_CNTL, in dccg314_set_dtbclk_p_src()
194 REG_UPDATE_2(DTBCLK_P_CNTL, in dccg314_set_dtbclk_p_src()
241 REG_UPDATE_2(OTG_PIXEL_RATE_CNTL[params->otg_inst], in dccg314_set_dtbclk_dto()
264 REG_UPDATE_2(DPSTREAMCLK_CNTL, in dccg314_set_dpstreamclk()
[all …]
/linux/drivers/gpu/drm/amd/display/dc/optc/dcn35/
H A Ddcn35_optc.c127 REG_UPDATE_2(OTG_CONTROL, in optc35_enable_crtc()
177 REG_UPDATE_2(OTG_CONTROL, OTG_DISABLE_POINT_CNTL, 0, OTG_MASTER_EN, 0); in optc35_phantom_crtc_post_enable()
292 REG_UPDATE_2(OTG_CRC0_WINDOWA_X_CONTROL, in optc35_configure_crc()
297 REG_UPDATE_2(OTG_CRC0_WINDOWA_Y_CONTROL, in optc35_configure_crc()
302 REG_UPDATE_2(OTG_CRC0_WINDOWB_X_CONTROL, in optc35_configure_crc()
307 REG_UPDATE_2(OTG_CRC0_WINDOWB_Y_CONTROL, in optc35_configure_crc()
325 REG_UPDATE_2(OTG_CRC1_WINDOWA_X_CONTROL, in optc35_configure_crc()
330 REG_UPDATE_2(OTG_CRC1_WINDOWA_Y_CONTROL, in optc35_configure_crc()
335 REG_UPDATE_2(OTG_CRC1_WINDOWB_X_CONTROL, in optc35_configure_crc()
340 REG_UPDATE_2(OTG_CRC1_WINDOWB_Y_CONTROL, in optc35_configure_crc()
[all …]
/linux/drivers/gpu/drm/amd/display/dc/optc/dcn20/
H A Ddcn20_optc.c69 REG_UPDATE_2(OTG_CONTROL, in optc2_enable_crtc()
315 REG_UPDATE_2(OTG_GLOBAL_CONTROL1, in optc2_align_vblanks()
361 REG_UPDATE_2(OTG_GLOBAL_CONTROL1, in optc2_align_vblanks()
417 REG_UPDATE_2(OTG_GLOBAL_CONTROL2, GLOBAL_UPDATE_LOCK_EN, 1, in optc2_lock_doublebuffer_enable()
424 REG_UPDATE_2(OTG_GLOBAL_CONTROL1, in optc2_lock_doublebuffer_enable()
440 REG_UPDATE_2(OTG_GLOBAL_CONTROL1, in optc2_lock_doublebuffer_disable()
446 REG_UPDATE_2(OTG_GLOBAL_CONTROL2, GLOBAL_UPDATE_LOCK_EN, 0, in optc2_lock_doublebuffer_disable()
/linux/drivers/gpu/drm/amd/display/dc/dcn30/
H A Ddcn30_afmt.c59 REG_UPDATE_2(AFMT_AUDIO_PACKET_CONTROL2, in afmt3_setup_hdmi_audio()
66 REG_UPDATE_2(AFMT_60958_0, in afmt3_setup_hdmi_audio()
181 REG_UPDATE_2(AFMT_AUDIO_PACKET_CONTROL2, in afmt3_setup_dp_audio()
/linux/drivers/gpu/drm/amd/display/dc/dcn31/
H A Ddcn31_vpg.c59 REG_UPDATE_2(VPG_MEM_PWR, VPG_GSP_MEM_LIGHT_SLEEP_DIS, 0, VPG_GSP_LIGHT_SLEEP_FORCE, 1); in vpg31_powerdown()
74 REG_UPDATE_2(VPG_MEM_PWR, VPG_GSP_MEM_LIGHT_SLEEP_DIS, 1, VPG_GSP_LIGHT_SLEEP_FORCE, 0); in vpg31_poweron()
H A Ddcn31_afmt.c64 REG_UPDATE_2(AFMT_MEM_PWR, AFMT_MEM_PWR_DIS, 0, AFMT_MEM_PWR_FORCE, 1); in afmt31_powerdown()
74 REG_UPDATE_2(AFMT_MEM_PWR, AFMT_MEM_PWR_DIS, 1, AFMT_MEM_PWR_FORCE, 0); in afmt31_poweron()
/linux/drivers/gpu/drm/amd/display/dc/hubp/dcn10/
H A Ddcn10_hubp.c46 REG_UPDATE_2(DCHUBP_CNTL, in hubp1_set_blank()
195 REG_UPDATE_2(DCSURF_SURFACE_PITCH, in hubp1_program_size()
199 REG_UPDATE_2(DCSURF_SURFACE_PITCH_C, in hubp1_program_size()
219 REG_UPDATE_2(DCSURF_SURFACE_CONFIG, in hubp1_program_rotation()
223 REG_UPDATE_2(DCSURF_SURFACE_CONFIG, in hubp1_program_rotation()
227 REG_UPDATE_2(DCSURF_SURFACE_CONFIG, in hubp1_program_rotation()
231 REG_UPDATE_2(DCSURF_SURFACE_CONFIG, in hubp1_program_rotation()
254 REG_UPDATE_2(HUBPRET_CONTROL, in hubp1_program_pixel_format()
332 REG_UPDATE_2(DCSURF_SURFACE_CONFIG, in hubp1_program_pixel_format()
337 REG_UPDATE_2(DCSURF_SURFACE_CONFIG, in hubp1_program_pixel_format()
[all …]
/linux/drivers/gpu/drm/amd/display/dc/optc/dcn30/
H A Ddcn30_optc.c80 REG_UPDATE_2(OTG_GLOBAL_CONTROL1, in optc3_lock_doublebuffer_enable()
83 REG_UPDATE_2(OTG_GLOBAL_CONTROL4, in optc3_lock_doublebuffer_enable()
106 REG_UPDATE_2(OTG_GLOBAL_CONTROL0, in optc3_lock_doublebuffer_disable()
109 REG_UPDATE_2(OTG_GLOBAL_CONTROL1, in optc3_lock_doublebuffer_disable()
/linux/drivers/gpu/drm/amd/display/dc/hubp/dcn401/
H A Ddcn401_hubp.c113 REG_UPDATE_2(_3DLUT_FL_BIAS_SCALE, HUBP0_3DLUT_FL_BIAS, bias, HUBP0_3DLUT_FL_SCALE, scale); in hubp401_update_3dlut_fl_bias_scale()
142 REG_UPDATE_2(_3DLUT_FL_CONFIG, in hubp401_program_3dlut_fl_config()
146 REG_UPDATE_2(_3DLUT_FL_BIAS_SCALE, in hubp401_program_3dlut_fl_config()
172 REG_UPDATE_2(DCHUBP_MALL_CONFIG, USE_MALL_SEL, mall_sel, in hubp401_update_mall_sel()
175 REG_UPDATE_2(DCHUBP_MALL_CONFIG, MALL_PREF_CMD_TYPE, 1, MALL_PREF_MODE, 0); in hubp401_update_mall_sel()
461 REG_UPDATE_2(DCSURF_SURFACE_CONTROL, in hubp401_program_surface_flip_and_addr()
530 REG_UPDATE_2(DCSURF_SURFACE_CONTROL, in hubp401_program_surface_flip_and_addr()
567 REG_UPDATE_2(DCSURF_SURFACE_CONTROL, in hubp401_clear_tiling()
577 REG_UPDATE_2(DCSURF_SURFACE_CONTROL, in hubp401_dcc_control()
/linux/drivers/gpu/drm/amd/display/dc/hubp/dcn20/
H A Ddcn20_hubp.c63 REG_UPDATE_2(DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB, in hubp2_set_vm_system_aperture_settings()
365 REG_UPDATE_2(DCSURF_SURFACE_PITCH, in hubp2_program_size()
372 REG_UPDATE_2(DCSURF_SURFACE_PITCH_C, in hubp2_program_size()
392 REG_UPDATE_2(DCSURF_SURFACE_CONFIG, in hubp2_program_rotation()
396 REG_UPDATE_2(DCSURF_SURFACE_CONFIG, in hubp2_program_rotation()
400 REG_UPDATE_2(DCSURF_SURFACE_CONFIG, in hubp2_program_rotation()
404 REG_UPDATE_2(DCSURF_SURFACE_CONFIG, in hubp2_program_rotation()
455 REG_UPDATE_2(HUBPRET_CONTROL, in hubp2_program_pixel_format()
533 REG_UPDATE_2(DCSURF_SURFACE_CONFIG, in hubp2_program_pixel_format()
538 REG_UPDATE_2(DCSURF_SURFACE_CONFIG, in hubp2_program_pixel_format()
[all …]
/linux/drivers/gpu/drm/amd/display/dc/hwss/dce/
H A Ddce_hwseq.c186 REG_UPDATE_2(PHYPLL_PIXEL_RATE_CNTL[tg_inst], in dce_crtc_switch_to_clk_src()
196 REG_UPDATE_2(PIXEL_RATE_CNTL[tg_inst], in dce_crtc_switch_to_clk_src()
/linux/drivers/gpu/drm/amd/display/dc/dccg/dcn20/
H A Ddcn20_dccg.c113 REG_UPDATE_2(OTG_PIXEL_RATE_CNTL[otg_inst], in dccg2_otg_add_pixel()
125 REG_UPDATE_2(OTG_PIXEL_RATE_CNTL[otg_inst], in dccg2_otg_drop_pixel()
/linux/drivers/gpu/drm/amd/display/dc/mpc/dcn20/
H A Ddcn20_mpc.c118 REG_UPDATE_2(DENORM_CONTROL[opp_id], in mpc2_set_denorm_clamp()
121 REG_UPDATE_2(DENORM_CLAMP_G_Y[opp_id], in mpc2_set_denorm_clamp()
124 REG_UPDATE_2(DENORM_CLAMP_B_CB[opp_id], in mpc2_set_denorm_clamp()
289 REG_UPDATE_2(MPCC_OGAM_LUT_RAM_CONTROL[mpcc_id], in mpc20_configure_ogam_lut()
/linux/drivers/gpu/drm/amd/display/dc/dcn20/
H A Ddcn20_dwb.c78 REG_UPDATE_2(CNV_SOURCE_SIZE, CNV_SOURCE_WIDTH, params->cnv_params.src_width, in dwb2_config_dwb_cnv()
256 REG_UPDATE_2(WBSCL_MODE, WBSCL_MODE, params->out_format, in dwb2_set_scaler()
/linux/drivers/gpu/drm/amd/display/dc/gpio/
H A Dhw_generic.c76 REG_UPDATE_2(mux, in set_config()

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