13f68c01bSZhan Liu /*
23f68c01bSZhan Liu * Copyright 2012-15 Advanced Micro Devices, Inc.
33f68c01bSZhan Liu *
43f68c01bSZhan Liu * Permission is hereby granted, free of charge, to any person obtaining a
53f68c01bSZhan Liu * copy of this software and associated documentation files (the "Software"),
63f68c01bSZhan Liu * to deal in the Software without restriction, including without limitation
73f68c01bSZhan Liu * the rights to use, copy, modify, merge, publish, distribute, sublicense,
83f68c01bSZhan Liu * and/or sell copies of the Software, and to permit persons to whom the
93f68c01bSZhan Liu * Software is furnished to do so, subject to the following conditions:
103f68c01bSZhan Liu *
113f68c01bSZhan Liu * The above copyright notice and this permission notice shall be included in
123f68c01bSZhan Liu * all copies or substantial portions of the Software.
133f68c01bSZhan Liu *
143f68c01bSZhan Liu * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
153f68c01bSZhan Liu * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
163f68c01bSZhan Liu * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
173f68c01bSZhan Liu * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
183f68c01bSZhan Liu * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
193f68c01bSZhan Liu * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
203f68c01bSZhan Liu * OTHER DEALINGS IN THE SOFTWARE.
213f68c01bSZhan Liu *
223f68c01bSZhan Liu * Authors: AMD
233f68c01bSZhan Liu *
243f68c01bSZhan Liu */
253f68c01bSZhan Liu
263f68c01bSZhan Liu #include "reg_helper.h"
273f68c01bSZhan Liu #include "dcn201_mpc.h"
283f68c01bSZhan Liu
293f68c01bSZhan Liu #define REG(reg)\
303f68c01bSZhan Liu mpc201->mpc_regs->reg
313f68c01bSZhan Liu
323f68c01bSZhan Liu #define CTX \
333f68c01bSZhan Liu mpc201->base.ctx
343f68c01bSZhan Liu
353f68c01bSZhan Liu #define DC_LOGGER \
363f68c01bSZhan Liu mpc201->base.ctx->logger
373f68c01bSZhan Liu
383f68c01bSZhan Liu #undef FN
393f68c01bSZhan Liu #define FN(reg_name, field_name) \
403f68c01bSZhan Liu mpc201->mpc_shift->field_name, mpc201->mpc_mask->field_name
413f68c01bSZhan Liu
mpc201_set_out_rate_control(struct mpc * mpc,int opp_id,bool enable,bool rate_2x_mode,struct mpc_dwb_flow_control * flow_control)423f68c01bSZhan Liu static void mpc201_set_out_rate_control(
433f68c01bSZhan Liu struct mpc *mpc,
443f68c01bSZhan Liu int opp_id,
453f68c01bSZhan Liu bool enable,
463f68c01bSZhan Liu bool rate_2x_mode,
473f68c01bSZhan Liu struct mpc_dwb_flow_control *flow_control)
483f68c01bSZhan Liu {
493f68c01bSZhan Liu struct dcn201_mpc *mpc201 = TO_DCN201_MPC(mpc);
503f68c01bSZhan Liu
513f68c01bSZhan Liu REG_UPDATE_2(MUX[opp_id],
523f68c01bSZhan Liu MPC_OUT_RATE_CONTROL_DISABLE, !enable,
533f68c01bSZhan Liu MPC_OUT_RATE_CONTROL, rate_2x_mode);
543f68c01bSZhan Liu
553f68c01bSZhan Liu if (flow_control)
563f68c01bSZhan Liu REG_UPDATE_3(MUX[opp_id],
573f68c01bSZhan Liu MPC_OUT_FLOW_CONTROL_MODE, flow_control->flow_ctrl_mode,
583f68c01bSZhan Liu MPC_OUT_FLOW_CONTROL_COUNT0, flow_control->flow_ctrl_cnt0,
593f68c01bSZhan Liu MPC_OUT_FLOW_CONTROL_COUNT1, flow_control->flow_ctrl_cnt1);
603f68c01bSZhan Liu }
613f68c01bSZhan Liu
mpc201_init_mpcc(struct mpcc * mpcc,int mpcc_inst)623f68c01bSZhan Liu static void mpc201_init_mpcc(struct mpcc *mpcc, int mpcc_inst)
633f68c01bSZhan Liu {
643f68c01bSZhan Liu mpcc->mpcc_id = mpcc_inst;
653f68c01bSZhan Liu mpcc->dpp_id = 0xf;
663f68c01bSZhan Liu mpcc->mpcc_bot = NULL;
673f68c01bSZhan Liu mpcc->blnd_cfg.overlap_only = false;
683f68c01bSZhan Liu mpcc->blnd_cfg.global_alpha = 0xff;
693f68c01bSZhan Liu mpcc->blnd_cfg.global_gain = 0xff;
703f68c01bSZhan Liu mpcc->blnd_cfg.background_color_bpc = 4;
713f68c01bSZhan Liu mpcc->blnd_cfg.bottom_gain_mode = 0;
723f68c01bSZhan Liu mpcc->blnd_cfg.top_gain = 0x1f000;
733f68c01bSZhan Liu mpcc->blnd_cfg.bottom_inside_gain = 0x1f000;
743f68c01bSZhan Liu mpcc->blnd_cfg.bottom_outside_gain = 0x1f000;
753f68c01bSZhan Liu mpcc->sm_cfg.enable = false;
763f68c01bSZhan Liu mpcc->shared_bottom = false;
773f68c01bSZhan Liu }
783f68c01bSZhan Liu
79*20ce5ed6STom Rix static const struct mpc_funcs dcn201_mpc_funcs = {
803f68c01bSZhan Liu .read_mpcc_state = mpc1_read_mpcc_state,
813f68c01bSZhan Liu .insert_plane = mpc1_insert_plane,
823f68c01bSZhan Liu .remove_mpcc = mpc1_remove_mpcc,
833f68c01bSZhan Liu .mpc_init = mpc1_mpc_init,
843f68c01bSZhan Liu .mpc_init_single_inst = mpc1_mpc_init_single_inst,
853f68c01bSZhan Liu .update_blending = mpc2_update_blending,
863f68c01bSZhan Liu .cursor_lock = mpc1_cursor_lock,
873f68c01bSZhan Liu .get_mpcc_for_dpp = mpc1_get_mpcc_for_dpp,
883f68c01bSZhan Liu .get_mpcc_for_dpp_from_secondary = NULL,
893f68c01bSZhan Liu .wait_for_idle = mpc2_assert_idle_mpcc,
903f68c01bSZhan Liu .assert_mpcc_idle_before_connect = mpc2_assert_mpcc_idle_before_connect,
913f68c01bSZhan Liu .init_mpcc_list_from_hw = mpc1_init_mpcc_list_from_hw,
923f68c01bSZhan Liu .set_denorm = mpc2_set_denorm,
933f68c01bSZhan Liu .set_denorm_clamp = mpc2_set_denorm_clamp,
943f68c01bSZhan Liu .set_output_csc = mpc2_set_output_csc,
953f68c01bSZhan Liu .set_ocsc_default = mpc2_set_ocsc_default,
963f68c01bSZhan Liu .set_output_gamma = mpc2_set_output_gamma,
973f68c01bSZhan Liu .set_out_rate_control = mpc201_set_out_rate_control,
983f68c01bSZhan Liu .power_on_mpc_mem_pwr = mpc20_power_on_ogam_lut,
993f68c01bSZhan Liu .get_mpc_out_mux = mpc1_get_mpc_out_mux,
1003f68c01bSZhan Liu .set_bg_color = mpc1_set_bg_color,
1013f68c01bSZhan Liu };
1023f68c01bSZhan Liu
dcn201_mpc_construct(struct dcn201_mpc * mpc201,struct dc_context * ctx,const struct dcn201_mpc_registers * mpc_regs,const struct dcn201_mpc_shift * mpc_shift,const struct dcn201_mpc_mask * mpc_mask,int num_mpcc)1033f68c01bSZhan Liu void dcn201_mpc_construct(struct dcn201_mpc *mpc201,
1043f68c01bSZhan Liu struct dc_context *ctx,
1053f68c01bSZhan Liu const struct dcn201_mpc_registers *mpc_regs,
1063f68c01bSZhan Liu const struct dcn201_mpc_shift *mpc_shift,
1073f68c01bSZhan Liu const struct dcn201_mpc_mask *mpc_mask,
1083f68c01bSZhan Liu int num_mpcc)
1093f68c01bSZhan Liu {
1103f68c01bSZhan Liu int i;
1113f68c01bSZhan Liu
1123f68c01bSZhan Liu mpc201->base.ctx = ctx;
1133f68c01bSZhan Liu
1143f68c01bSZhan Liu mpc201->base.funcs = &dcn201_mpc_funcs;
1153f68c01bSZhan Liu
1163f68c01bSZhan Liu mpc201->mpc_regs = mpc_regs;
1173f68c01bSZhan Liu mpc201->mpc_shift = mpc_shift;
1183f68c01bSZhan Liu mpc201->mpc_mask = mpc_mask;
1193f68c01bSZhan Liu
1203f68c01bSZhan Liu mpc201->mpcc_in_use_mask = 0;
1213f68c01bSZhan Liu mpc201->num_mpcc = num_mpcc;
1223f68c01bSZhan Liu
1233f68c01bSZhan Liu for (i = 0; i < MAX_MPCC; i++)
1243f68c01bSZhan Liu mpc201_init_mpcc(&mpc201->base.mpcc_array[i], i);
1253f68c01bSZhan Liu }
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