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Searched refs:REG_READ (Results 1 – 25 of 46) sorted by relevance

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/linux/drivers/gpu/drm/gma500/
H A Dgma_display.c93 dspcntr = REG_READ(map->cntr); in gma_pipe_set_base()
125 REG_READ(map->base); in gma_pipe_set_base()
128 REG_READ(map->base); in gma_pipe_set_base()
130 REG_READ(map->surf); in gma_pipe_set_base()
223 temp = REG_READ(map->dpll); in gma_crtc_dpms()
226 REG_READ(map->dpll); in gma_crtc_dpms()
230 REG_READ(map->dpll); in gma_crtc_dpms()
234 REG_READ(map->dpll); in gma_crtc_dpms()
240 temp = REG_READ(map->cntr); in gma_crtc_dpms()
245 REG_WRITE(map->base, REG_READ(map->base)); in gma_crtc_dpms()
[all …]
H A Dcdv_intel_display.c135 ret = wait_for((REG_READ(SB_PCKT) & SB_BUSY) == 0, 1000); in cdv_sb_read()
147 ret = wait_for((REG_READ(SB_PCKT) & SB_BUSY) == 0, 1000); in cdv_sb_read()
153 *val = REG_READ(SB_DATA); in cdv_sb_read()
170 ret = wait_for((REG_READ(SB_PCKT) & SB_BUSY) == 0, 1000); in cdv_sb_write()
183 ret = wait_for((REG_READ(SB_PCKT) & SB_BUSY) == 0, 1000); in cdv_sb_write()
204 REG_READ(DPIO_CFG); in cdv_sb_reset()
473 if (REG_READ(FW_BLC_SELF) & FW_BLC_SELF_EN) { in cdv_disable_sr()
476 REG_WRITE(FW_BLC_SELF, (REG_READ(FW_BLC_SELF) & ~FW_BLC_SELF_EN)); in cdv_disable_sr()
477 REG_READ(FW_BLC_SELF); in cdv_disable_sr()
485 REG_READ(OV_OVADD); in cdv_disable_sr()
[all …]
H A Dpsb_intel_display.c85 pfit_control = REG_READ(PFIT_CONTROL); in psb_intel_panel_fitter_pipe()
198 pipeconf = REG_READ(map->conf); in psb_intel_crtc_mode_set()
222 REG_READ(map->dpll); in psb_intel_crtc_mode_set()
231 u32 lvds = REG_READ(LVDS); in psb_intel_crtc_mode_set()
252 REG_READ(LVDS); in psb_intel_crtc_mode_set()
257 REG_READ(map->dpll); in psb_intel_crtc_mode_set()
264 REG_READ(map->dpll); in psb_intel_crtc_mode_set()
289 REG_READ(map->conf); in psb_intel_crtc_mode_set()
318 dpll = REG_READ(map->dpll); in psb_intel_crtc_clock_get()
320 fp = REG_READ(map->fp0); in psb_intel_crtc_clock_get()
[all …]
H A Dintel_i2c.c29 val = REG_READ(chan->reg); in get_clock()
39 val = REG_READ(chan->reg); in get_data()
51 REG_READ(chan->reg) & (GPIO_DATA_PULLUP_DISABLE | in set_clock()
71 REG_READ(chan->reg) & (GPIO_DATA_PULLUP_DISABLE | in set_data()
H A Dpsb_irq.c237 REG_WRITE(PORT_HOTPLUG_STAT, REG_READ(PORT_HOTPLUG_STAT)); in gma_irq_handler()
387 reg_val = REG_READ(pipeconf_reg); in gma_crtc_enable_vblank()
465 reg_val = REG_READ(pipeconf_reg); in gma_crtc_get_vblank_counter()
479 high1 = ((REG_READ(high_frame) & PIPE_FRAME_HIGH_MASK) >> in gma_crtc_get_vblank_counter()
481 low = ((REG_READ(low_frame) & PIPE_FRAME_LOW_MASK) >> in gma_crtc_get_vblank_counter()
483 high2 = ((REG_READ(high_frame) & PIPE_FRAME_HIGH_MASK) >> in gma_crtc_get_vblank_counter()
/linux/drivers/net/wireless/ath/ath9k/
H A Dar9002_calib.c88 if (!(REG_READ(ah, AR_PHY_TIMING_CTRL4(0)) & in ar9002_hw_per_calibration()
131 REG_READ(ah, AR_PHY_CAL_MEAS_0(i)); in ar9002_hw_iqcal_collect()
133 REG_READ(ah, AR_PHY_CAL_MEAS_1(i)); in ar9002_hw_iqcal_collect()
135 (int32_t) REG_READ(ah, AR_PHY_CAL_MEAS_2(i)); in ar9002_hw_iqcal_collect()
150 REG_READ(ah, AR_PHY_CAL_MEAS_0(i)); in ar9002_hw_adc_gaincal_collect()
152 REG_READ(ah, AR_PHY_CAL_MEAS_1(i)); in ar9002_hw_adc_gaincal_collect()
154 REG_READ(ah, AR_PHY_CAL_MEAS_2(i)); in ar9002_hw_adc_gaincal_collect()
156 REG_READ(ah, AR_PHY_CAL_MEAS_3(i)); in ar9002_hw_adc_gaincal_collect()
174 (int32_t) REG_READ(ah, AR_PHY_CAL_MEAS_0(i)); in ar9002_hw_adc_dccal_collect()
176 (int32_t) REG_READ(ah, AR_PHY_CAL_MEAS_1(i)); in ar9002_hw_adc_dccal_collect()
[all …]
H A Dar9003_calib.c83 if (REG_READ(ah, AR_PHY_TIMING4) & AR_PHY_TIMING4_DO_CAL) in ar9003_hw_per_calibration()
183 REG_READ(ah, AR_PHY_CAL_MEAS_0(i)); in ar9003_hw_iqcal_collect()
185 REG_READ(ah, AR_PHY_CAL_MEAS_1(i)); in ar9003_hw_iqcal_collect()
187 (int32_t) REG_READ(ah, AR_PHY_CAL_MEAS_2(i)); in ar9003_hw_iqcal_collect()
271 REG_READ(ah, offset_array[i])); in ar9003_hw_iqcalibrate()
288 REG_READ(ah, offset_array[i])); in ar9003_hw_iqcalibrate()
293 REG_READ(ah, offset_array[i])); in ar9003_hw_iqcalibrate()
306 REG_READ(ah, AR_PHY_RX_IQCAL_CORR_B0)); in ar9003_hw_iqcalibrate()
354 REG_READ(ah, AR_PHY_AGC_CONTROL(ah)) | AR_PHY_AGC_CONTROL_CAL); in ar9003_hw_dynamic_osdac_selection()
384 osdac_ch0 = (REG_READ(ah, AR_PHY_65NM_CH0_BB1) >> 30) & 0x3; in ar9003_hw_dynamic_osdac_selection()
[all …]
H A Dar9003_wow.c48 REG_READ(ah, AR_CR), REG_READ(ah, AR_DIAG_SW)); in ath9k_hw_set_powermode_wow_sleep()
53 if (!REG_READ(ah, AR_MAC_PCU_GEN_TIMER_TSF_SEL)) in ath9k_hw_set_powermode_wow_sleep()
56 if (!(REG_READ(ah, AR_NDP2_TIMER_MODE) & in ath9k_hw_set_powermode_wow_sleep()
192 rval = REG_READ(ah, AR_WOW_PATTERN); in ath9k_hw_wow_wakeup()
213 rval = REG_READ(ah, AR_MAC_PCU_WOW4); in ath9k_hw_wow_wakeup()
236 AR_WOW_CLEAR_EVENTS(REG_READ(ah, AR_WOW_PATTERN))); in ath9k_hw_wow_wakeup()
238 AR_WOW_CLEAR_EVENTS2(REG_READ(ah, AR_MAC_PCU_WOW4))); in ath9k_hw_wow_wakeup()
256 u32 dc = REG_READ(ah, AR_DIRECT_CONNECT); in ath9k_hw_wow_wakeup()
281 wa_reg = REG_READ(ah, AR_WA(ah)); in ath9k_hw_wow_set_arwr_reg()
364 keep_alive = REG_READ(ah, AR_WOW_KEEP_ALIVE); in ath9k_hw_wow_enable()
[all …]
H A Dar9002_phy.c76 reg32 = REG_READ(ah, AR_PHY_SYNTH_CONTROL); in ar9002_hw_set_channel()
98 txctl = REG_READ(ah, AR_PHY_CCK_TX_CTRL); in ar9002_hw_set_channel()
225 tmp = REG_READ(ah, AR_PHY_TIMING_CTRL4(0)); in ar9002_hw_spur_mitigate()
298 MS(REG_READ(ah, AR_PHY_TX_GAIN_TBL1 + i * 4), in ar9002_olc_init()
336 nf = MS(REG_READ(ah, AR_PHY_CCA), AR9280_PHY_MINCCA_PWR); in ar9002_hw_do_getnf()
339 nf = MS(REG_READ(ah, AR_PHY_EXT_CCA), AR9280_PHY_EXT_MINCCA_PWR); in ar9002_hw_do_getnf()
346 nf = MS(REG_READ(ah, AR_PHY_CH1_CCA), AR9280_PHY_CH1_MINCCA_PWR); in ar9002_hw_do_getnf()
349 nf = MS(REG_READ(ah, AR_PHY_CH1_EXT_CCA), AR9280_PHY_CH1_EXT_MINCCA_PWR); in ar9002_hw_do_getnf()
383 regval = REG_READ(ah, AR_PHY_MULTICHAIN_GAIN_CTL); in ar9002_hw_antdiv_comb_conf_get()
400 regval = REG_READ(ah, AR_PHY_MULTICHAIN_GAIN_CTL); in ar9002_hw_antdiv_comb_conf_set()
[all …]
H A Dmac.c48 return REG_READ(ah, AR_QTXDP(q)); in ath9k_hw_gettxbuf()
69 npend = REG_READ(ah, AR_QSTS(q)) & AR_Q_STS_PEND_FR_CNT; in ath9k_hw_numtxpending()
72 if (REG_READ(ah, AR_Q_TXE) & (1 << q)) in ath9k_hw_numtxpending()
114 txcfg = REG_READ(ah, AR_TXCFG); in ath9k_hw_updatetxtriglevel()
653 reg = REG_READ(ah, AR_OBS_BUS_1); in ath9k_hw_setrxabort()
710 if ((REG_READ(ah, AR_CR) & AR_CR_RXE(ah)) == 0) in ath9k_hw_stopdmarecv()
714 mac_status = REG_READ(ah, AR_DMADBG_7) & 0x7f0; in ath9k_hw_stopdmarecv()
730 REG_READ(ah, AR_CR), in ath9k_hw_stopdmarecv()
731 REG_READ(ah, AR_DIAG_SW), in ath9k_hw_stopdmarecv()
732 REG_READ(ah, AR_DMADBG_7)); in ath9k_hw_stopdmarecv()
[all …]
H A Dar5008_phy.c233 txctl = REG_READ(ah, AR_PHY_CCK_TX_CTRL); in ar5008_hw_set_channel()
462 tmp = REG_READ(ah, AR_PHY_TIMING_CTRL4(0)); in ar5008_hw_spur_mitigate()
583 synthDelay = REG_READ(ah, AR_PHY_RX_DELAY) & AR_PHY_RX_DELAY_DELAY; in ar5008_hw_init_bb()
632 REG_READ(ah, AR_PHY_ANALOG_SWAP) | 0x00000001); in ar5008_hw_init_chain_masks()
655 val = REG_READ(ah, AR_PCU_MISC_MODE2) & in ar5008_hw_override_ini()
682 val = REG_READ(ah, AR_PHY_HEAVY_CLIP_FACTOR_RIFS); in ar5008_hw_override_ini()
695 enableDacFifo = (REG_READ(ah, AR_PHY_TURBO) & in ar5008_hw_set_channel_regs()
896 u32 synthDelay = REG_READ(ah, AR_PHY_RX_DELAY) & AR_PHY_RX_DELAY_DELAY; in ar5008_hw_rfbus_done()
1142 nf = MS(REG_READ(ah, AR_PHY_CCA), AR_PHY_MINCCA_PWR); in ar5008_hw_do_getnf()
1145 nf = MS(REG_READ(ah, AR_PHY_CH1_CCA), AR_PHY_CH1_MINCCA_PWR); in ar5008_hw_do_getnf()
[all …]
H A Drng.c37 v1 = REG_READ(ah, AR_PHY_TST_ADC) & 0xffff; in ath9k_rng_data_read()
38 v2 = REG_READ(ah, AR_PHY_TST_ADC) & 0xffff; in ath9k_rng_data_read()
H A Deeprom_9287.c320 tmpVal = REG_READ(ah, 0xa270); in ar9287_eeprom_olpc_set_pdadcs()
327 tmpVal = REG_READ(ah, 0xb270); in ar9287_eeprom_olpc_set_pdadcs()
335 tmpVal = REG_READ(ah, 0xa398); in ar9287_eeprom_olpc_set_pdadcs()
345 tmpVal = REG_READ(ah, 0xb398); in ar9287_eeprom_olpc_set_pdadcs()
374 pdGainOverlap_t2 = (u16)(MS(REG_READ(ah, AR_PHY_TPCRG5), in ath9k_hw_set_ar9287_power_cal_table()
869 (REG_READ(ah, AR_PHY_TIMING_CTRL4(0) + regChainOffset) in ath9k_hw_ar9287_set_board_values()
918 regval = REG_READ(ah, AR9287_AN_RF2G3_CH0); in ath9k_hw_ar9287_set_board_values()
934 regval = REG_READ(ah, AR9287_AN_RF2G3_CH1); in ath9k_hw_ar9287_set_board_values()
/linux/drivers/net/wireless/ath/
H A Dhw.c23 #define REG_READ (common->ops->read) macro
124 id1 = REG_READ(ah, AR_STA_ID1) & ~AR_STA_ID1_SADH_MASK; in ath_hw_setbssidmask()
151 cycles = REG_READ(ah, AR_CCCNT); in ath_hw_cycle_counters_update()
152 busy = REG_READ(ah, AR_RCCNT); in ath_hw_cycle_counters_update()
153 rx = REG_READ(ah, AR_RFCNT); in ath_hw_cycle_counters_update()
154 tx = REG_READ(ah, AR_TFCNT); in ath_hw_cycle_counters_update()
/linux/drivers/gpu/drm/amd/display/dc/dcn301/
H A Ddcn301_panel_cntl.c128 REG_READ(BL_PWM_CNTL); in dcn301_panel_cntl_hw_init()
130 REG_READ(BL_PWM_CNTL2); in dcn301_panel_cntl_hw_init()
132 REG_READ(BL_PWM_PERIOD_CNTL); in dcn301_panel_cntl_hw_init()
185 REG_READ(BL_PWM_CNTL); in dcn301_store_backlight_level()
187 REG_READ(BL_PWM_CNTL2); in dcn301_store_backlight_level()
189 REG_READ(BL_PWM_PERIOD_CNTL); in dcn301_store_backlight_level()
/linux/drivers/input/keyboard/
H A Dgoldfish_events.c19 REG_READ = 0x00, enumerator
41 type = __raw_readl(edev->addr + REG_READ); in events_interrupt()
42 code = __raw_readl(edev->addr + REG_READ); in events_interrupt()
43 value = __raw_readl(edev->addr + REG_READ); in events_interrupt()
/linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn30/
H A Ddcn30m_clk_mgr_smu_msg.c59 reg = REG_READ(DAL_RESP_REG); in dcn30m_smu_wait_for_response()
100 *param_out = REG_READ(DAL_ARG_REG); in dcn30m_smu_send_msg_with_param()
/linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/
H A Ddcn35_clk_mgr.c452 actual_dtbclk = REG_READ(CLK1_CLK4_CURRENT_CNT); in dcn35_update_clocks()
614 internal->CLK1_CLK4_CURRENT_CNT = REG_READ(CLK1_CLK4_CURRENT_CNT); in dcn35_save_clk_registers_internal()
615 internal->CLK1_CLK4_BYPASS_CNTL = REG_READ(CLK1_CLK4_BYPASS_CNTL); in dcn35_save_clk_registers_internal()
618 internal->CLK1_CLK3_CURRENT_CNT = REG_READ(CLK1_CLK3_CURRENT_CNT); in dcn35_save_clk_registers_internal()
619 internal->CLK1_CLK3_BYPASS_CNTL = REG_READ(CLK1_CLK3_BYPASS_CNTL); in dcn35_save_clk_registers_internal()
622 internal->CLK1_CLK3_DS_CNTL = REG_READ(CLK1_CLK3_DS_CNTL); in dcn35_save_clk_registers_internal()
623 internal->CLK1_CLK3_ALLOW_DS = REG_READ(CLK1_CLK3_ALLOW_DS); in dcn35_save_clk_registers_internal()
626 internal->CLK1_CLK1_CURRENT_CNT = REG_READ(CLK1_CLK1_CURRENT_CNT); in dcn35_save_clk_registers_internal()
627 internal->CLK1_CLK1_BYPASS_CNTL = REG_READ(CLK1_CLK1_BYPASS_CNTL); in dcn35_save_clk_registers_internal()
630 internal->CLK1_CLK2_CURRENT_CNT = REG_READ(CLK1_CLK2_CURRENT_CNT); in dcn35_save_clk_registers_internal()
[all …]
/linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn301/
H A Ddcn301_smu.c85 res_val = REG_READ(MP1_SMN_C2PMSG_91); in dcn301_smu_wait_for_response()
130 return REG_READ(MP1_SMN_C2PMSG_83); in dcn301_smu_send_msg_with_param()
/linux/arch/x86/mm/
H A Dpf_in.h13 REG_READ, /* read from addr to reg */ enumerator
/linux/drivers/media/usb/dvb-usb-v2/
H A Dce6230.h32 REG_READ = 0xde, /* rd e */ enumerator
/linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn316/
H A Ddcn316_smu.c105 res_val = REG_READ(MP1_SMN_C2PMSG_91); in dcn316_smu_wait_for_response()
149 return REG_READ(MP1_SMN_C2PMSG_83); in dcn316_smu_send_msg_with_param()
/linux/drivers/net/wireless/st/cw1200/
H A Dfwio.c86 #define REG_READ(reg, val) \ in cw1200_load_firmware_cw1200() macro
136 REG_READ(ST90TDS_CONFIG_REG_ID, val32); in cw1200_load_firmware_cw1200()
261 #undef REG_READ in cw1200_load_firmware_cw1200()
/linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn314/
H A Ddcn314_smu.c106 res_val = REG_READ(MP1_SMN_C2PMSG_91); in dcn314_smu_wait_for_response()
163 return REG_READ(MP1_SMN_C2PMSG_83); in dcn314_smu_send_msg_with_param()
/linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/
H A Ddcn31_smu.c90 res_val = REG_READ(MP1_SMN_C2PMSG_91); in dcn31_smu_wait_for_response()
144 return REG_READ(MP1_SMN_C2PMSG_83); in dcn31_smu_send_msg_with_param()

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