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Searched refs:REG_READ (Results 1 – 25 of 89) sorted by relevance

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/linux/drivers/gpu/drm/amd/display/dc/hubp/dcn30/
H A Ddcn30_hubp.c469 s->uclk_pstate_force = REG_READ(UCLK_PSTATE_FORCE); in hubp3_read_state()
472 s->hubp_cntl = REG_READ(DCHUBP_CNTL); in hubp3_read_state()
475 s->flip_control = REG_READ(DCSURF_FLIP_CONTROL); in hubp3_read_state()
483 reg_state->hubp_cntl = REG_READ(DCHUBP_CNTL); in hubp3_read_reg_state()
484 reg_state->mall_config = REG_READ(DCHUBP_MALL_CONFIG); in hubp3_read_reg_state()
485 reg_state->mall_sub_vp = REG_READ(DCHUBP_MALL_SUB_VP); in hubp3_read_reg_state()
486 reg_state->hubp_req_size_config = REG_READ(DCHUBP_REQ_SIZE_CONFIG); in hubp3_read_reg_state()
487 reg_state->hubp_req_size_config_c = REG_READ(DCHUBP_REQ_SIZE_CONFIG_C); in hubp3_read_reg_state()
488 reg_state->vmpg_config = REG_READ(DCHUBP_VMPG_CONFIG); in hubp3_read_reg_state()
489 reg_state->addr_config = REG_READ(DCSURF_ADDR_CONFIG); in hubp3_read_reg_state()
[all …]
/linux/drivers/gpu/drm/amd/display/dc/dccg/dcn31/
H A Ddcn31_dccg.c717 dccg_reg_state->dc_mem_global_pwr_req_cntl = REG_READ(DC_MEM_GLOBAL_PWR_REQ_CNTL); in dccg31_read_reg_state()
718 dccg_reg_state->dccg_audio_dtbclk_dto_modulo = REG_READ(DCCG_AUDIO_DTBCLK_DTO_MODULO); in dccg31_read_reg_state()
719 dccg_reg_state->dccg_audio_dtbclk_dto_phase = REG_READ(DCCG_AUDIO_DTBCLK_DTO_PHASE); in dccg31_read_reg_state()
720 dccg_reg_state->dccg_audio_dto_source = REG_READ(DCCG_AUDIO_DTO_SOURCE); in dccg31_read_reg_state()
721 dccg_reg_state->dccg_audio_dto0_module = REG_READ(DCCG_AUDIO_DTO0_MODULE); in dccg31_read_reg_state()
722 dccg_reg_state->dccg_audio_dto0_phase = REG_READ(DCCG_AUDIO_DTO0_PHASE); in dccg31_read_reg_state()
723 dccg_reg_state->dccg_audio_dto1_module = REG_READ(DCCG_AUDIO_DTO1_MODULE); in dccg31_read_reg_state()
724 dccg_reg_state->dccg_audio_dto1_phase = REG_READ(DCCG_AUDIO_DTO1_PHASE); in dccg31_read_reg_state()
725 dccg_reg_state->dccg_cac_status = REG_READ(DCCG_CAC_STATUS); in dccg31_read_reg_state()
726 dccg_reg_state->dccg_cac_status2 = REG_READ(DCCG_CAC_STATUS2); in dccg31_read_reg_state()
[all …]
/linux/drivers/gpu/drm/gma500/
H A Dgma_display.c93 dspcntr = REG_READ(map->cntr); in gma_pipe_set_base()
125 REG_READ(map->base); in gma_pipe_set_base()
128 REG_READ(map->base); in gma_pipe_set_base()
130 REG_READ(map->surf); in gma_pipe_set_base()
223 temp = REG_READ(map->dpll); in gma_crtc_dpms()
226 REG_READ(map->dpll); in gma_crtc_dpms()
230 REG_READ(map->dpll); in gma_crtc_dpms()
234 REG_READ(map->dpll); in gma_crtc_dpms()
240 temp = REG_READ(map->cntr); in gma_crtc_dpms()
245 REG_WRITE(map->base, REG_READ(map->base)); in gma_crtc_dpms()
[all …]
H A Dcdv_intel_display.c135 ret = wait_for((REG_READ(SB_PCKT) & SB_BUSY) == 0, 1000); in cdv_sb_read()
147 ret = wait_for((REG_READ(SB_PCKT) & SB_BUSY) == 0, 1000); in cdv_sb_read()
153 *val = REG_READ(SB_DATA); in cdv_sb_read()
170 ret = wait_for((REG_READ(SB_PCKT) & SB_BUSY) == 0, 1000); in cdv_sb_write()
183 ret = wait_for((REG_READ(SB_PCKT) & SB_BUSY) == 0, 1000); in cdv_sb_write()
204 REG_READ(DPIO_CFG); in cdv_sb_reset()
473 if (REG_READ(FW_BLC_SELF) & FW_BLC_SELF_EN) { in cdv_disable_sr()
476 REG_WRITE(FW_BLC_SELF, (REG_READ(FW_BLC_SELF) & ~FW_BLC_SELF_EN)); in cdv_disable_sr()
477 REG_READ(FW_BLC_SELF); in cdv_disable_sr()
485 REG_READ(OV_OVADD); in cdv_disable_sr()
[all …]
H A Dpsb_intel_lvds.c68 ret = REG_READ(BLC_PWM_CTL); in psb_intel_lvds_get_max_backlight()
80 REG_READ(BLC_PWM_CTL), dev_priv->regs.saveBLC_PWM_CTL); in psb_intel_lvds_get_max_backlight()
190 blc_pwm_ctl = REG_READ(BLC_PWM_CTL); in psb_intel_lvds_set_backlight()
221 REG_WRITE(PP_CONTROL, REG_READ(PP_CONTROL) | in psb_intel_lvds_set_power()
224 pp_status = REG_READ(PP_STATUS); in psb_intel_lvds_set_power()
232 REG_WRITE(PP_CONTROL, REG_READ(PP_CONTROL) & in psb_intel_lvds_set_power()
235 pp_status = REG_READ(PP_STATUS); in psb_intel_lvds_set_power()
262 lvds_priv->savePP_ON = REG_READ(LVDSPP_ON); in psb_intel_lvds_save()
263 lvds_priv->savePP_OFF = REG_READ(LVDSPP_OFF); in psb_intel_lvds_save()
264 lvds_priv->saveLVDS = REG_READ(LVDS); in psb_intel_lvds_save()
[all …]
H A Doaktrail_hdmi.c296 dpll = REG_READ(DPLL_CTRL); in oaktrail_crtc_hdmi_mode_set()
312 dpll = REG_READ(DPLL_CTRL); in oaktrail_crtc_hdmi_mode_set()
360 dspcntr = REG_READ(dspcntr_reg); in oaktrail_crtc_hdmi_mode_set()
366 pipeconf = REG_READ(pipeconf_reg); in oaktrail_crtc_hdmi_mode_set()
370 REG_READ(pipeconf_reg); in oaktrail_crtc_hdmi_mode_set()
373 REG_READ(PCH_PIPEBCONF); in oaktrail_crtc_hdmi_mode_set()
396 temp = REG_READ(DSPBCNTR); in oaktrail_crtc_hdmi_dpms()
399 REG_READ(DSPBCNTR); in oaktrail_crtc_hdmi_dpms()
401 REG_WRITE(DSPBSURF, REG_READ(DSPBSURF)); in oaktrail_crtc_hdmi_dpms()
402 REG_READ(DSPBSURF); in oaktrail_crtc_hdmi_dpms()
[all …]
H A Dpsb_intel_display.c85 pfit_control = REG_READ(PFIT_CONTROL); in psb_intel_panel_fitter_pipe()
198 pipeconf = REG_READ(map->conf); in psb_intel_crtc_mode_set()
222 REG_READ(map->dpll); in psb_intel_crtc_mode_set()
231 u32 lvds = REG_READ(LVDS); in psb_intel_crtc_mode_set()
252 REG_READ(LVDS); in psb_intel_crtc_mode_set()
257 REG_READ(map->dpll); in psb_intel_crtc_mode_set()
264 REG_READ(map->dpll); in psb_intel_crtc_mode_set()
289 REG_READ(map->conf); in psb_intel_crtc_mode_set()
318 dpll = REG_READ(map->dpll); in psb_intel_crtc_clock_get()
320 fp = REG_READ(map->fp0); in psb_intel_crtc_clock_get()
[all …]
H A Dcdv_intel_dp.c389 pp = REG_READ(PP_CONTROL); in cdv_intel_edp_panel_vdd_on()
393 REG_READ(PP_CONTROL); in cdv_intel_edp_panel_vdd_on()
403 pp = REG_READ(PP_CONTROL); in cdv_intel_edp_panel_vdd_off()
407 REG_READ(PP_CONTROL); in cdv_intel_edp_panel_vdd_off()
422 pp = REG_READ(PP_CONTROL); in cdv_intel_edp_panel_on()
427 REG_READ(PP_CONTROL); in cdv_intel_edp_panel_on()
429 if (wait_for(((REG_READ(PP_STATUS) & idle_on_mask) == idle_on_mask), 1000)) { in cdv_intel_edp_panel_on()
430 DRM_DEBUG_KMS("Error in Powering up eDP panel, status %x\n", REG_READ(PP_STATUS)); in cdv_intel_edp_panel_on()
447 pp = REG_READ(PP_CONTROL); in cdv_intel_edp_panel_off()
460 REG_READ(PP_CONTROL); in cdv_intel_edp_panel_off()
[all …]
H A Dintel_i2c.c29 val = REG_READ(chan->reg); in get_clock()
39 val = REG_READ(chan->reg); in get_data()
51 REG_READ(chan->reg) & (GPIO_DATA_PULLUP_DISABLE | in set_clock()
71 REG_READ(chan->reg) & (GPIO_DATA_PULLUP_DISABLE | in set_data()
H A Dcdv_intel_crt.c49 temp = REG_READ(reg); in cdv_intel_crt_dpms()
112 dpll_md = REG_READ(dpll_md_reg); in cdv_intel_crt_mode_set()
152 orig = hotplug_en = REG_READ(PORT_HOTPLUG_EN); in cdv_intel_crt_detect_hotplug()
166 if (!(REG_READ(PORT_HOTPLUG_EN) & in cdv_intel_crt_detect_hotplug()
173 if ((REG_READ(PORT_HOTPLUG_STAT) & CRT_HOTPLUG_MONITOR_MASK) != in cdv_intel_crt_detect_hotplug()
H A Dcdv_intel_lvds.c67 retval = ((REG_READ(BLC_PWM_CTL) & in cdv_intel_lvds_get_max_backlight()
92 REG_READ(BLC_PWM_CTL) & ~BACKLIGHT_DUTY_CYCLE_MASK; in cdv_intel_lvds_set_backlight()
118 REG_WRITE(PP_CONTROL, REG_READ(PP_CONTROL) | in cdv_intel_lvds_set_power()
121 pp_status = REG_READ(PP_STATUS); in cdv_intel_lvds_set_power()
129 REG_WRITE(PP_CONTROL, REG_READ(PP_CONTROL) & in cdv_intel_lvds_set_power()
132 pp_status = REG_READ(PP_STATUS); in cdv_intel_lvds_set_power()
239 mode_dev->saveBLC_PWM_CTL = REG_READ(BLC_PWM_CTL); in cdv_intel_lvds_prepare()
613 lvds = REG_READ(LVDS); in cdv_intel_lvds_init()
638 pwm = REG_READ(BLC_PWM_CTL2); in cdv_intel_lvds_init()
/linux/drivers/gpu/drm/amd/display/dc/hubbub/dcn20/
H A Ddcn20_hubbub.c517 s->data_urgent = REG_READ(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_A); in hubbub2_wm_read_state()
519 s->pte_meta_urgent = REG_READ(DCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_A); in hubbub2_wm_read_state()
521 s->sr_enter = REG_READ(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_A); in hubbub2_wm_read_state()
522 s->sr_exit = REG_READ(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_A); in hubbub2_wm_read_state()
524 s->dram_clk_change = REG_READ(DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_A); in hubbub2_wm_read_state()
528 s->data_urgent = REG_READ(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_B); in hubbub2_wm_read_state()
530 s->pte_meta_urgent = REG_READ(DCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_B); in hubbub2_wm_read_state()
532 s->sr_enter = REG_READ(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_B); in hubbub2_wm_read_state()
533 s->sr_exit = REG_READ(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_B); in hubbub2_wm_read_state()
535 s->dram_clk_change = REG_READ(DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_B); in hubbub2_wm_read_state()
[all …]
/linux/drivers/net/wireless/ath/ath9k/
H A Dar9002_calib.c88 if (!(REG_READ(ah, AR_PHY_TIMING_CTRL4(0)) & in ar9002_hw_per_calibration()
131 REG_READ(ah, AR_PHY_CAL_MEAS_0(i)); in ar9002_hw_iqcal_collect()
133 REG_READ(ah, AR_PHY_CAL_MEAS_1(i)); in ar9002_hw_iqcal_collect()
135 (int32_t) REG_READ(ah, AR_PHY_CAL_MEAS_2(i)); in ar9002_hw_iqcal_collect()
150 REG_READ(ah, AR_PHY_CAL_MEAS_0(i)); in ar9002_hw_adc_gaincal_collect()
152 REG_READ(ah, AR_PHY_CAL_MEAS_1(i)); in ar9002_hw_adc_gaincal_collect()
154 REG_READ(ah, AR_PHY_CAL_MEAS_2(i)); in ar9002_hw_adc_gaincal_collect()
156 REG_READ(ah, AR_PHY_CAL_MEAS_3(i)); in ar9002_hw_adc_gaincal_collect()
174 (int32_t) REG_READ(ah, AR_PHY_CAL_MEAS_0(i)); in ar9002_hw_adc_dccal_collect()
176 (int32_t) REG_READ(ah, AR_PHY_CAL_MEAS_1(i)); in ar9002_hw_adc_dccal_collect()
[all …]
H A Dar9003_calib.c83 if (REG_READ(ah, AR_PHY_TIMING4) & AR_PHY_TIMING4_DO_CAL) in ar9003_hw_per_calibration()
183 REG_READ(ah, AR_PHY_CAL_MEAS_0(i)); in ar9003_hw_iqcal_collect()
185 REG_READ(ah, AR_PHY_CAL_MEAS_1(i)); in ar9003_hw_iqcal_collect()
187 (int32_t) REG_READ(ah, AR_PHY_CAL_MEAS_2(i)); in ar9003_hw_iqcal_collect()
271 REG_READ(ah, offset_array[i])); in ar9003_hw_iqcalibrate()
288 REG_READ(ah, offset_array[i])); in ar9003_hw_iqcalibrate()
293 REG_READ(ah, offset_array[i])); in ar9003_hw_iqcalibrate()
306 REG_READ(ah, AR_PHY_RX_IQCAL_CORR_B0)); in ar9003_hw_iqcalibrate()
354 REG_READ(ah, AR_PHY_AGC_CONTROL(ah)) | AR_PHY_AGC_CONTROL_CAL); in ar9003_hw_dynamic_osdac_selection()
384 osdac_ch0 = (REG_READ(ah, AR_PHY_65NM_CH0_BB1) >> 30) & 0x3; in ar9003_hw_dynamic_osdac_selection()
[all …]
H A Dar9003_wow.c48 REG_READ(ah, AR_CR), REG_READ(ah, AR_DIAG_SW)); in ath9k_hw_set_powermode_wow_sleep()
53 if (!REG_READ(ah, AR_MAC_PCU_GEN_TIMER_TSF_SEL)) in ath9k_hw_set_powermode_wow_sleep()
56 if (!(REG_READ(ah, AR_NDP2_TIMER_MODE) & in ath9k_hw_set_powermode_wow_sleep()
192 rval = REG_READ(ah, AR_WOW_PATTERN); in ath9k_hw_wow_wakeup()
213 rval = REG_READ(ah, AR_MAC_PCU_WOW4); in ath9k_hw_wow_wakeup()
236 AR_WOW_CLEAR_EVENTS(REG_READ(ah, AR_WOW_PATTERN))); in ath9k_hw_wow_wakeup()
238 AR_WOW_CLEAR_EVENTS2(REG_READ(ah, AR_MAC_PCU_WOW4))); in ath9k_hw_wow_wakeup()
256 u32 dc = REG_READ(ah, AR_DIRECT_CONNECT); in ath9k_hw_wow_wakeup()
281 wa_reg = REG_READ(ah, AR_WA(ah)); in ath9k_hw_wow_set_arwr_reg()
364 keep_alive = REG_READ(ah, AR_WOW_KEEP_ALIVE); in ath9k_hw_wow_enable()
[all …]
H A Dar9002_mac.c43 if (REG_READ(ah, AR_INTR_ASYNC_CAUSE(ah)) & AR_INTR_MAC_IRQ) { in ar9002_hw_get_isr()
44 if ((REG_READ(ah, AR_RTC_STATUS(ah)) & AR_RTC_STATUS_M(ah)) in ar9002_hw_get_isr()
46 isr = REG_READ(ah, AR_ISR); in ar9002_hw_get_isr()
50 sync_cause = REG_READ(ah, AR_INTR_SYNC_CAUSE(ah)) & in ar9002_hw_get_isr()
59 isr = REG_READ(ah, AR_ISR); in ar9002_hw_get_isr()
65 isr2 = REG_READ(ah, AR_ISR_S2); in ar9002_hw_get_isr()
88 isr = REG_READ(ah, AR_ISR_RAC); in ar9002_hw_get_isr()
109 s0_s = REG_READ(ah, AR_ISR_S0_S); in ar9002_hw_get_isr()
110 s1_s = REG_READ(ah, AR_ISR_S1_S); in ar9002_hw_get_isr()
112 s0_s = REG_READ(ah, AR_ISR_S0); in ar9002_hw_get_isr()
[all …]
H A Dar9002_phy.c76 reg32 = REG_READ(ah, AR_PHY_SYNTH_CONTROL); in ar9002_hw_set_channel()
98 txctl = REG_READ(ah, AR_PHY_CCK_TX_CTRL); in ar9002_hw_set_channel()
225 tmp = REG_READ(ah, AR_PHY_TIMING_CTRL4(0)); in ar9002_hw_spur_mitigate()
298 MS(REG_READ(ah, AR_PHY_TX_GAIN_TBL1 + i * 4), in ar9002_olc_init()
336 nf = MS(REG_READ(ah, AR_PHY_CCA), AR9280_PHY_MINCCA_PWR); in ar9002_hw_do_getnf()
339 nf = MS(REG_READ(ah, AR_PHY_EXT_CCA), AR9280_PHY_EXT_MINCCA_PWR); in ar9002_hw_do_getnf()
346 nf = MS(REG_READ(ah, AR_PHY_CH1_CCA), AR9280_PHY_CH1_MINCCA_PWR); in ar9002_hw_do_getnf()
349 nf = MS(REG_READ(ah, AR_PHY_CH1_EXT_CCA), AR9280_PHY_CH1_EXT_MINCCA_PWR); in ar9002_hw_do_getnf()
383 regval = REG_READ(ah, AR_PHY_MULTICHAIN_GAIN_CTL); in ar9002_hw_antdiv_comb_conf_get()
400 regval = REG_READ(ah, AR_PHY_MULTICHAIN_GAIN_CTL); in ar9002_hw_antdiv_comb_conf_set()
[all …]
H A Dmac.c48 return REG_READ(ah, AR_QTXDP(q)); in ath9k_hw_gettxbuf()
69 npend = REG_READ(ah, AR_QSTS(q)) & AR_Q_STS_PEND_FR_CNT; in ath9k_hw_numtxpending()
72 if (REG_READ(ah, AR_Q_TXE) & (1 << q)) in ath9k_hw_numtxpending()
114 txcfg = REG_READ(ah, AR_TXCFG); in ath9k_hw_updatetxtriglevel()
653 reg = REG_READ(ah, AR_OBS_BUS_1); in ath9k_hw_setrxabort()
710 if ((REG_READ(ah, AR_CR) & AR_CR_RXE(ah)) == 0) in ath9k_hw_stopdmarecv()
714 mac_status = REG_READ(ah, AR_DMADBG_7) & 0x7f0; in ath9k_hw_stopdmarecv()
730 REG_READ(ah, AR_CR), in ath9k_hw_stopdmarecv()
731 REG_READ(ah, AR_DIAG_SW), in ath9k_hw_stopdmarecv()
732 REG_READ(ah, AR_DMADBG_7)); in ath9k_hw_stopdmarecv()
[all …]
H A Dar9003_phy.c617 (REG_READ(ah, AR_PHY_GEN_CTRL) & AR_PHY_GC_ENABLE_DAC_FIFO); in ar9003_hw_set_channel_regs()
635 phymode |= REG_READ(ah, AR_PHY_GEN_CTRL); in ar9003_hw_set_channel_regs()
660 synthDelay = REG_READ(ah, AR_PHY_RX_DELAY) & AR_PHY_RX_DELAY_DELAY; in ar9003_hw_init_bb()
703 val = REG_READ(ah, AR_PCU_MISC_MODE2) & (~AR_ADHOC_MCAST_KEYID_ENABLE); in ar9003_hw_override_ini()
721 if (REG_READ(ah, AR_PHY_CL_CAL_CTL) & AR_PHY_CL_CAL_ENABLE) in ar9003_hw_override_ini()
1055 u32 synthDelay = REG_READ(ah, AR_PHY_RX_DELAY) & AR_PHY_RX_DELAY_DELAY; in ar9003_hw_rfbus_done()
1349 nf = MS(REG_READ(ah, ah->nf_regs[i]), in ar9003_hw_do_getnf()
1356 nf = MS(REG_READ(ah, ah->nf_regs[ext_idx]), in ar9003_hw_do_getnf()
1406 val = REG_READ(ah, AR_PHY_SFCORR); in ar9003_hw_ani_cache_ini_regs()
1411 val = REG_READ(ah, AR_PHY_SFCORR_LOW); in ar9003_hw_ani_cache_ini_regs()
[all …]
H A Dhw.c84 if ((REG_READ(ah, reg) & mask) == val) in ath9k_hw_wait()
92 timeout, reg, REG_READ(ah, reg), mask, val); in ath9k_hw_wait()
270 val = REG_READ(ah, AR_SREV(ah)); in ath9k_hw_read_revisions()
288 srev = REG_READ(ah, AR_SREV(ah)); in ath9k_hw_read_revisions()
365 regHold[i] = REG_READ(ah, addr); in ath9k_hw_chip_test()
369 rdData = REG_READ(ah, addr); in ath9k_hw_chip_test()
380 rdData = REG_READ(ah, addr); in ath9k_hw_chip_test()
610 ah->WARegVal = REG_READ(ah, AR_WA(ah)); in __ath9k_hw_init()
641 ah->hw_version.phyRev = REG_READ(ah, AR_PHY_CHIP_ID); in __ath9k_hw_init()
745 while ((REG_READ(ah, PLL4) & PLL4_MEAS_DONE) == 0) { in ar9003_get_pll_sqsum_dvc()
[all …]
H A Dar5008_phy.c233 txctl = REG_READ(ah, AR_PHY_CCK_TX_CTRL); in ar5008_hw_set_channel()
462 tmp = REG_READ(ah, AR_PHY_TIMING_CTRL4(0)); in ar5008_hw_spur_mitigate()
583 synthDelay = REG_READ(ah, AR_PHY_RX_DELAY) & AR_PHY_RX_DELAY_DELAY; in ar5008_hw_init_bb()
632 REG_READ(ah, AR_PHY_ANALOG_SWAP) | 0x00000001); in ar5008_hw_init_chain_masks()
655 val = REG_READ(ah, AR_PCU_MISC_MODE2) & in ar5008_hw_override_ini()
682 val = REG_READ(ah, AR_PHY_HEAVY_CLIP_FACTOR_RIFS); in ar5008_hw_override_ini()
695 enableDacFifo = (REG_READ(ah, AR_PHY_TURBO) & in ar5008_hw_set_channel_regs()
896 u32 synthDelay = REG_READ(ah, AR_PHY_RX_DELAY) & AR_PHY_RX_DELAY_DELAY; in ar5008_hw_rfbus_done()
1142 nf = MS(REG_READ(ah, AR_PHY_CCA), AR_PHY_MINCCA_PWR); in ar5008_hw_do_getnf()
1145 nf = MS(REG_READ(ah, AR_PHY_CH1_CCA), AR_PHY_CH1_MINCCA_PWR); in ar5008_hw_do_getnf()
[all …]
/linux/drivers/net/wireless/ath/
H A Dhw.c23 #define REG_READ (common->ops->read) macro
124 id1 = REG_READ(ah, AR_STA_ID1) & ~AR_STA_ID1_SADH_MASK; in ath_hw_setbssidmask()
151 cycles = REG_READ(ah, AR_CCCNT); in ath_hw_cycle_counters_update()
152 busy = REG_READ(ah, AR_RCCNT); in ath_hw_cycle_counters_update()
153 rx = REG_READ(ah, AR_RFCNT); in ath_hw_cycle_counters_update()
154 tx = REG_READ(ah, AR_TFCNT); in ath_hw_cycle_counters_update()
/linux/drivers/gpu/drm/amd/display/dc/dce/
H A Ddce_panel_cntl.c57 REG_READ(BL_PWM_PERIOD_CNTL); in dce_get_16_bit_backlight_from_pwm()
61 REG_READ(BL_PWM_CNTL); in dce_get_16_bit_backlight_from_pwm()
113 REG_READ(BL_PWM_CNTL); in dce_panel_cntl_hw_init()
115 REG_READ(BL_PWM_CNTL2); in dce_panel_cntl_hw_init()
117 REG_READ(BL_PWM_PERIOD_CNTL); in dce_panel_cntl_hw_init()
131 value = REG_READ(BIOS_SCRATCH_2); in dce_panel_cntl_hw_init()
178 REG_READ(BL_PWM_CNTL); in dce_store_backlight_level()
180 REG_READ(BL_PWM_CNTL2); in dce_store_backlight_level()
182 REG_READ(BL_PWM_PERIOD_CNTL); in dce_store_backlight_level()
/linux/drivers/gpu/drm/amd/display/dc/dcn301/
H A Ddcn301_panel_cntl.c128 REG_READ(BL_PWM_CNTL); in dcn301_panel_cntl_hw_init()
130 REG_READ(BL_PWM_CNTL2); in dcn301_panel_cntl_hw_init()
132 REG_READ(BL_PWM_PERIOD_CNTL); in dcn301_panel_cntl_hw_init()
185 REG_READ(BL_PWM_CNTL); in dcn301_store_backlight_level()
187 REG_READ(BL_PWM_CNTL2); in dcn301_store_backlight_level()
189 REG_READ(BL_PWM_PERIOD_CNTL); in dcn301_store_backlight_level()
/linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/
H A Ddcn32_clk_mgr.c530 dispclk_khz_reg = REG_READ(CLK1_CLK0_CURRENT_CNT); // DISPCLK in dcn32_auto_dpm_test_log()
531 dppclk_khz_reg = REG_READ(CLK1_CLK1_CURRENT_CNT); // DPPCLK in dcn32_auto_dpm_test_log()
532 dprefclk_khz_reg = REG_READ(CLK1_CLK2_CURRENT_CNT); // DPREFCLK in dcn32_auto_dpm_test_log()
533 dcfclk_khz_reg = REG_READ(CLK1_CLK3_CURRENT_CNT); // DCFCLK in dcn32_auto_dpm_test_log()
534 dtbclk_khz_reg = REG_READ(CLK1_CLK4_CURRENT_CNT); // DTBCLK in dcn32_auto_dpm_test_log()
535 fclk_khz_reg = REG_READ(CLK4_CLK0_CURRENT_CNT); // FCLK in dcn32_auto_dpm_test_log()
855 pll_req_reg = REG_READ(CLK0_CLK_PLL_REQ); in dcn32_get_vco_frequency_from_reg()
857 pll_req_reg = REG_READ(CLK1_CLK_PLL_REQ); in dcn32_get_vco_frequency_from_reg()
885 dispclk_did = REG_READ(CLK0_CLK0_DFS_CNTL); in dcn32_dump_clk_registers()
887 dppclk_did = REG_READ(CLK0_CLK1_DFS_CNTL); in dcn32_dump_clk_registers()
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