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Searched refs:REG_GET (Results 1 – 25 of 25) sorted by relevance

/linux/drivers/gpu/drm/amd/display/dc/dcn301/
H A Ddcn301_panel_cntl.c57 REG_GET(BL_PWM_PERIOD_CNTL, BL_PWM_PERIOD, &bl_period); in dcn301_get_16_bit_backlight_from_pwm()
58 REG_GET(BL_PWM_PERIOD_CNTL, BL_PWM_PERIOD_BITCNT, &bl_int_count); in dcn301_get_16_bit_backlight_from_pwm()
60 REG_GET(BL_PWM_CNTL, BL_ACTIVE_INT_FRAC_CNT, &bl_pwm); in dcn301_get_16_bit_backlight_from_pwm()
61 REG_GET(BL_PWM_CNTL, BL_PWM_FRACTIONAL_EN, &fractional_duty_cycle_en); in dcn301_get_16_bit_backlight_from_pwm()
106 REG_GET(BL_PWM_CNTL, BL_ACTIVE_INT_FRAC_CNT, &value); in dcn301_panel_cntl_hw_init()
134 REG_GET(PWRSEQ_REF_DIV, BL_PWM_REF_DIV, in dcn301_panel_cntl_hw_init()
163 REG_GET(PWRSEQ_CNTL, PANEL_BLON, &value); in dcn301_is_panel_backlight_on()
173 REG_GET(PWRSEQ_STATE, PANEL_PWRSEQ_TARGET_STATE_R, &pwr_seq_state); in dcn301_is_panel_powered_on()
191 REG_GET(PWRSEQ_REF_DIV, BL_PWM_REF_DIV, in dcn301_store_backlight_level()
/linux/drivers/gpu/drm/amd/display/dc/dcn20/
H A Ddcn20_dwb.c177 REG_GET(CNV_UPDATE, CNV_UPDATE_LOCK, &pre_locked); in dwb2_update()
204 REG_GET(WB_ENABLE, WB_ENABLE, &wb_enabled); in dwb2_is_enabled()
205 REG_GET(CNV_MODE, CNV_FRAME_CAPTURE_EN, &cnv_frame_capture_en); in dwb2_is_enabled()
H A Ddcn20_vmid.c61 REG_GET(PAGE_TABLE_BASE_ADDR_LO32, in dcn20_wait_for_vmid_ready()
/linux/drivers/gpu/drm/omapdrm/dss/
H A Dhdmi4_core.c43 if (REG_GET(base, HDMI_CORE_DDC_STATUS, 4, 4) == 1) { in hdmi4_core_ddc_init()
110 if (REG_GET(base, HDMI_CORE_DDC_STATUS, 6, 6) == 1) { in hdmi4_core_ddc_read()
115 if (REG_GET(base, HDMI_CORE_DDC_STATUS, 5, 5) == 1) { in hdmi4_core_ddc_read()
124 if (REG_GET(base, HDMI_CORE_DDC_STATUS, 4, 4) == 0) { in hdmi4_core_ddc_read()
131 while (REG_GET(base, HDMI_CORE_DDC_STATUS, 2, 2) == 1) { in hdmi4_core_ddc_read()
139 buf[i] = REG_GET(base, HDMI_CORE_DDC_DATA, 7, 0); in hdmi4_core_ddc_read()
H A Dhdmi.h280 #define REG_GET(base, idx, start, end) \ macro
287 while (val != (v = REG_GET(base_addr, idx, b2, b1))) { in hdmi_wait_for_bit_change()
H A Dhdmi_wp.c70 if (REG_GET(wp->base, HDMI_WP_PWR_CTRL, 5, 4) == val) in hdmi_wp_set_phy_pwr()
H A Ddispc.c50 #define REG_GET(dispc, idx, start, end) \ macro
371 return REG_GET(dispc, rfld->reg, rfld->high, rfld->low); in mgr_fld_read()
1353 size = REG_GET(dispc, DISPC_OVL_FIFO_SIZE_STATUS(fifo), in dispc_init_fifos()
1451 REG_GET(dispc, DISPC_OVL_FIFO_THRESHOLD(plane), in dispc_ovl_set_fifo_threshold()
1453 REG_GET(dispc, DISPC_OVL_FIFO_THRESHOLD(plane), in dispc_ovl_set_fifo_threshold()
3210 lcd = REG_GET(dispc, DISPC_DIVISORo(channel), 23, 16); in dispc_mgr_lclk_rate()
4529 gatestate = REG_GET(dispc, DISPC_CONFIG, 8, 4); in dispc_errata_i734_wa()
4745 if (REG_GET(dispc, DISPC_CONFIG, 2, 1) != OMAP_DSS_LOAD_FRAME_ONLY) { in dispc_runtime_resume()
H A Ddss.c55 #define REG_GET(dss, idx, start, end) \ macro
/linux/drivers/video/fbdev/omap2/omapfb/dss/
H A Dhdmi4_core.c44 if (REG_GET(base, HDMI_CORE_DDC_STATUS, 4, 4) == 1) { in hdmi_core_ddc_init()
116 if (REG_GET(base, HDMI_CORE_DDC_STATUS, 6, 6) == 1) { in hdmi_core_ddc_edid()
121 if (REG_GET(base, HDMI_CORE_DDC_STATUS, 5, 5) == 1) { in hdmi_core_ddc_edid()
130 if (REG_GET(base, HDMI_CORE_DDC_STATUS, 4, 4) == 0) { in hdmi_core_ddc_edid()
137 while (REG_GET(base, HDMI_CORE_DDC_STATUS, 2, 2) == 1) { in hdmi_core_ddc_edid()
145 pedid[i] = REG_GET(base, HDMI_CORE_DDC_DATA, 7, 0); in hdmi_core_ddc_edid()
H A Dhdmi.h261 #define REG_GET(base, idx, start, end) \ macro
268 while (val != (v = REG_GET(base_addr, idx, b2, b1))) { in hdmi_wait_for_bit_change()
H A Dhdmi5.c317 idlemode = REG_GET(hdmi.wp.base, HDMI_WP_SYSCONFIG, 3, 2); in read_edid()
701 REG_GET(hdmi.wp.base, HDMI_WP_SYSCONFIG, 3, 2); in hdmi_audio_register()
H A Dhdmi_wp.c71 if (REG_GET(wp->base, HDMI_WP_PWR_CTRL, 5, 4) == val) in hdmi_wp_set_phy_pwr()
H A Ddss.c56 #define REG_GET(idx, start, end) \ macro
650 return REG_GET(DSS_CONTROL, 15, 15); in dss_get_hdmi_venc_clk_source()
/linux/drivers/gpu/drm/amd/display/dc/bios/
H A Dbios_parser_helper.c64 REG_GET(BIOS_SCRATCH_6, S6_ACC_MODE, &acc_mode); in bios_is_accelerated_mode()
/linux/drivers/gpu/drm/amd/display/dc/dcn31/
H A Ddcn31_vpg.c68 REG_GET(VPG_MEM_PWR, VPG_GSP_MEM_PWR_STATE, &vpg_gsp_mem_pwr_state); in vpg31_poweron()
/linux/drivers/gpu/drm/amd/display/dc/hwss/dcn302/
H A Ddcn302_hwseq.c171 REG_GET(DC_IP_REQUEST_CNTL, IP_REQUEST_EN, &org_ip_request_cntl); in dcn302_dsc_pg_control()
/linux/drivers/gpu/drm/amd/display/dmub/src/
H A Ddmub_reg.h111 #define REG_GET(reg_name, field, val) \ macro
/linux/drivers/gpu/drm/amd/display/dc/optc/dcn201/
H A Ddcn201_optc.c126 REG_GET(OPTC_DATA_SOURCE_SELECT, in optc201_get_optc_source()
/linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn314/
H A Ddcn314_clk_mgr.c182 REG_GET(CLK6_0_CLK6_spll_field_8, spll_ssc_en, &ssc_enable); in dcn314_is_spll_ssc_enabled()
352 REG_GET(CLK1_CLK_PLL_REQ, FbMult_frac, &fbmult_frac_val); /* 16 bit fractional part*/ in get_vco_frequency_from_reg()
353 REG_GET(CLK1_CLK_PLL_REQ, FbMult_int, &fbmult_int_val); /* 8 bit integer part */ in get_vco_frequency_from_reg()
784 REG_GET(CLK1_CLK2_BYPASS_CNTL, CLK2_BYPASS_SEL, &clock_source); in dcn314_read_ss_info_from_lut()
/linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn201/
H A Ddcn201_clk_mgr.c206 REG_GET(CLK4_CLK_PLL_REQ, FbMult_int, &clk_mgr->base.dentist_vco_freq_khz); in dcn201_clk_mgr_construct()
/linux/drivers/gpu/drm/amd/display/dc/dce/
H A Ddce_stream_encoder.c930 REG_GET(DP_VID_STREAM_CNTL, DP_VID_STREAM_ENABLE, &reg1); in dce110_stream_encoder_dp_blank()
1531 REG_GET(DAC_SOURCE_SELECT, DAC_SOURCE_SELECT, &tg_inst); in dig_source_otg()
1533 REG_GET(DIG_FE_CNTL, DIG_SOURCE_SELECT, &tg_inst); in dig_source_otg()
/linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/
H A Ddcn31_clk_mgr.c273 REG_GET(CLK1_CLK_PLL_REQ, FbMult_frac, &fbmult_frac_val); /* 16 bit fractional part*/ in get_vco_frequency_from_reg()
274 REG_GET(CLK1_CLK_PLL_REQ, FbMult_int, &fbmult_int_val); /* 8 bit integer part */ in get_vco_frequency_from_reg()
/linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/
H A Ddcn35_clk_mgr.c564 REG_GET(CLK1_CLK_PLL_REQ, FbMult_frac, &fbmult_frac_val); /* 16 bit fractional part*/ in get_vco_frequency_from_reg()
565 REG_GET(CLK1_CLK_PLL_REQ, FbMult_int, &fbmult_int_val); /* 8 bit integer part */ in get_vco_frequency_from_reg()
/linux/drivers/gpu/drm/amd/display/dc/resource/dce100/
H A Ddce100_resource.c459 REG_GET(DC_PINSTRAPS, DC_PINSTRAPS_AUDIO, &straps->dc_pinstraps_audio); in read_dce_straps()
/linux/drivers/gpu/drm/amd/display/dc/resource/dce60/
H A Ddce60_resource.c494 REG_GET(DC_PINSTRAPS, DC_PINSTRAPS_AUDIO, &straps->dc_pinstraps_audio); in read_dce_straps()