Home
last modified time | relevance | path

Searched refs:REG_GET (Results 1 – 25 of 70) sorted by relevance

123

/linux/drivers/gpu/drm/amd/display/dc/hubp/dcn20/
H A Ddcn20_hubp.c724 REG_GET(DMDATA_STATUS, DMDATA_DONE, &status); in hubp2_dmdata_status_done()
899 REG_GET(DCSURF_FLIP_CONTROL2, SURFACE_TRIPLE_BUFFER_ENABLE, &triple_buffer_en); in hubp2_enable_triplebuffer()
913 REG_GET(DCSURF_FLIP_CONTROL2, SURFACE_TRIPLE_BUFFER_ENABLE, &triple_buffer_en); in hubp2_is_triplebuffer_enabled()
934 REG_GET(DCSURF_FLIP_CONTROL, in hubp2_is_flip_pending()
937 REG_GET(DCSURF_SURFACE_EARLIEST_INUSE, in hubp2_is_flip_pending()
940 REG_GET(DCSURF_SURFACE_EARLIEST_INUSE_HIGH, in hubp2_is_flip_pending()
1147 REG_GET(HUBPRET_CONTROL, in hubp2_read_state_common()
1155 REG_GET(DCN_VM_SYSTEM_APERTURE_HIGH_ADDR, in hubp2_read_state_common()
1158 REG_GET(DCN_VM_SYSTEM_APERTURE_LOW_ADDR, in hubp2_read_state_common()
1166 REG_GET(BLANK_OFFSET_1, in hubp2_read_state_common()
[all …]
/linux/drivers/gpu/drm/amd/display/dc/hubp/dcn10/
H A Ddcn10_hubp.c95 REG_GET(DCHUBP_CNTL, in hubp1_get_underflow_status()
761 REG_GET(DCSURF_FLIP_CONTROL, in hubp1_is_flip_pending()
764 REG_GET(DCSURF_SURFACE_EARLIEST_INUSE, in hubp1_is_flip_pending()
767 REG_GET(DCSURF_SURFACE_EARLIEST_INUSE_HIGH, in hubp1_is_flip_pending()
900 REG_GET(HUBPRET_CONTROL, in hubp1_read_state_common()
908 REG_GET(DCN_VM_SYSTEM_APERTURE_LOW_ADDR_MSB, in hubp1_read_state_common()
911 REG_GET(DCN_VM_SYSTEM_APERTURE_LOW_ADDR_LSB, in hubp1_read_state_common()
914 REG_GET(DCN_VM_SYSTEM_APERTURE_HIGH_ADDR_MSB, in hubp1_read_state_common()
917 REG_GET(DCN_VM_SYSTEM_APERTURE_HIGH_ADDR_LSB, in hubp1_read_state_common()
929 REG_GET(BLANK_OFFSET_1, in hubp1_read_state_common()
[all …]
/linux/drivers/gpu/drm/amd/display/dc/pg/dcn35/
H A Ddcn35_pg_cntl.c57 REG_GET(DOMAIN16_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, &pwr_status); in pg_cntl35_dsc_pg_status()
60 REG_GET(DOMAIN17_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, &pwr_status); in pg_cntl35_dsc_pg_status()
63 REG_GET(DOMAIN18_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, &pwr_status); in pg_cntl35_dsc_pg_status()
66 REG_GET(DOMAIN19_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, &pwr_status); in pg_cntl35_dsc_pg_status()
99 REG_GET(DC_IP_REQUEST_CNTL, IP_REQUEST_EN, &org_ip_request_cntl); in pg_cntl35_dsc_pg_control()
153 REG_GET(DOMAIN0_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, &pwr_status); in pg_cntl35_hubp_dpp_pg_status()
157 REG_GET(DOMAIN1_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, &pwr_status); in pg_cntl35_hubp_dpp_pg_status()
161 REG_GET(DOMAIN2_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, &pwr_status); in pg_cntl35_hubp_dpp_pg_status()
165 REG_GET(DOMAIN3_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, &pwr_status); in pg_cntl35_hubp_dpp_pg_status()
199 REG_GET(DC_IP_REQUEST_CNTL, IP_REQUEST_EN, &org_ip_request_cntl); in pg_cntl35_hubp_dpp_pg_control()
[all …]
/linux/drivers/gpu/drm/amd/display/dc/dcn301/
H A Ddcn301_panel_cntl.c57 REG_GET(BL_PWM_PERIOD_CNTL, BL_PWM_PERIOD, &bl_period); in dcn301_get_16_bit_backlight_from_pwm()
58 REG_GET(BL_PWM_PERIOD_CNTL, BL_PWM_PERIOD_BITCNT, &bl_int_count); in dcn301_get_16_bit_backlight_from_pwm()
60 REG_GET(BL_PWM_CNTL, BL_ACTIVE_INT_FRAC_CNT, &bl_pwm); in dcn301_get_16_bit_backlight_from_pwm()
61 REG_GET(BL_PWM_CNTL, BL_PWM_FRACTIONAL_EN, &fractional_duty_cycle_en); in dcn301_get_16_bit_backlight_from_pwm()
106 REG_GET(BL_PWM_CNTL, BL_ACTIVE_INT_FRAC_CNT, &value); in dcn301_panel_cntl_hw_init()
134 REG_GET(PWRSEQ_REF_DIV, BL_PWM_REF_DIV, in dcn301_panel_cntl_hw_init()
163 REG_GET(PWRSEQ_CNTL, PANEL_BLON, &value); in dcn301_is_panel_backlight_on()
173 REG_GET(PWRSEQ_STATE, PANEL_PWRSEQ_TARGET_STATE_R, &pwr_seq_state); in dcn301_is_panel_powered_on()
191 REG_GET(PWRSEQ_REF_DIV, BL_PWM_REF_DIV, in dcn301_store_backlight_level()
/linux/drivers/gpu/drm/amd/display/dc/hubp/dcn401/
H A Ddcn401_hubp.c71 REG_GET(HUBP_3DLUT_CONTROL, HUBP_3DLUT_DONE, &ret); in hubp401_get_3dlut_fl_done()
725 REG_GET(DCHUBP_CNTL, HUBP_IN_BLANK, &in_blank); in hubp401_in_blank()
831 REG_GET(HUBPRET_CONTROL, in hubp401_read_state()
853 REG_GET(DCN_VM_SYSTEM_APERTURE_HIGH_ADDR, in hubp401_read_state()
856 REG_GET(DCN_VM_SYSTEM_APERTURE_LOW_ADDR, in hubp401_read_state()
864 REG_GET(BLANK_OFFSET_1, in hubp401_read_state()
867 REG_GET(DST_DIMENSIONS, in hubp401_read_state()
882 REG_GET(REF_FREQ_TO_PIX_FREQ, in hubp401_read_state()
886 REG_GET(VBLANK_PARAMETERS_1, in hubp401_read_state()
889 REG_GET(VBLANK_PARAMETERS_3, in hubp401_read_state()
[all …]
/linux/drivers/gpu/drm/amd/display/dc/dce/
H A Ddce_panel_cntl.c58 REG_GET(BL_PWM_PERIOD_CNTL, BL_PWM_PERIOD, &bl_period); in dce_get_16_bit_backlight_from_pwm()
59 REG_GET(BL_PWM_PERIOD_CNTL, BL_PWM_PERIOD_BITCNT, &bl_int_count); in dce_get_16_bit_backlight_from_pwm()
62 REG_GET(BL_PWM_CNTL, BL_ACTIVE_INT_FRAC_CNT, (uint32_t *)(&bl_pwm)); in dce_get_16_bit_backlight_from_pwm()
63 REG_GET(BL_PWM_CNTL, BL_PWM_FRACTIONAL_EN, &fractional_duty_cycle_en); in dce_get_16_bit_backlight_from_pwm()
99 REG_GET(BL_PWM_CNTL, BL_ACTIVE_INT_FRAC_CNT, &value); in dce_panel_cntl_hw_init()
119 REG_GET(PWRSEQ_REF_DIV, BL_PWM_REF_DIV, in dce_panel_cntl_hw_init()
153 REG_GET(PWRSEQ_CNTL, LVTMA_PWRSEQ_TARGET_STATE, &pwrseq_target_state); in dce_is_panel_backlight_on()
166 REG_GET(PWRSEQ_STATE, LVTMA_PWRSEQ_TARGET_STATE_R, &pwr_seq_state); in dce_is_panel_powered_on()
184 REG_GET(PWRSEQ_REF_DIV, BL_PWM_REF_DIV, in dce_store_backlight_level()
/linux/drivers/gpu/drm/amd/display/dc/optc/dcn35/
H A Ddcn35_optc.c212 REG_GET(OTG_CRC_CNTL, OTG_CRC_EN, &field); in optc35_get_crc()
224 REG_GET(OTG_CRC0_DATA_R32, in optc35_get_crc()
226 REG_GET(OTG_CRC0_DATA_G32, in optc35_get_crc()
228 REG_GET(OTG_CRC0_DATA_B32, in optc35_get_crc()
233 REG_GET(OTG_CRC1_DATA_R32, in optc35_get_crc()
235 REG_GET(OTG_CRC1_DATA_G32, in optc35_get_crc()
237 REG_GET(OTG_CRC1_DATA_B32, in optc35_get_crc()
252 REG_GET(OTG_CRC0_DATA_B, in optc35_get_crc()
262 REG_GET(OTG_CRC1_DATA_B, in optc35_get_crc()
537 REG_GET(OTG_CONTROL, OTG_MASTER_EN, &is_master_en); in optc35_wait_otg_disable()
/linux/drivers/gpu/drm/amd/display/dc/optc/dcn20/
H A Ddcn20_optc.c157 REG_GET(OPTC_DATA_FORMAT_CONTROL, in optc2_get_dsc_status()
281 REG_GET(OTG_H_TOTAL, OTG_H_TOTAL, &slave_h_total); in optc2_align_vblanks()
291 REG_GET(OTG_MASTER_UPDATE_LOCK, in optc2_align_vblanks()
297 REG_GET(OTG_V_BLANK_START_END, in optc2_align_vblanks()
299 REG_GET(OTG_H_TOTAL, OTG_H_TOTAL, &master_h_total); in optc2_align_vblanks()
420 REG_GET(OTG_V_BLANK_START_END, OTG_V_BLANK_START, &v_blank_start); in optc2_lock_doublebuffer_enable()
422 REG_GET(OTG_H_BLANK_START_END, OTG_H_BLANK_START, &h_blank_start); in optc2_lock_doublebuffer_enable()
502 REG_GET(OTG_DRR_CONTROL, OTG_V_TOTAL_LAST_USED_BY_DRR, refresh_rate); in optc2_get_last_used_drr_vtotal()
/linux/drivers/gpu/drm/amd/display/dc/gpio/
H A Dhw_gpio.c45 REG_GET(MASK_reg, MASK, &gpio->store.mask); in store_registers()
46 REG_GET(A_reg, A, &gpio->store.a); in store_registers()
47 REG_GET(EN_reg, EN, &gpio->store.en); in store_registers()
86 REG_GET(Y_reg, Y, value); in dal_hw_gpio_get_value()
/linux/drivers/gpu/drm/amd/display/dc/hubbub/dcn401/
H A Ddcn401_hubbub.c48 REG_GET(DCHUBBUB_DET0_CTRL, DET0_SIZE_CURRENT, in dcn401_init_crb()
51 REG_GET(DCHUBBUB_DET1_CTRL, DET1_SIZE_CURRENT, in dcn401_init_crb()
54 REG_GET(DCHUBBUB_DET2_CTRL, DET2_SIZE_CURRENT, in dcn401_init_crb()
57 REG_GET(DCHUBBUB_DET3_CTRL, DET3_SIZE_CURRENT, in dcn401_init_crb()
60 REG_GET(DCHUBBUB_COMPBUF_CTRL, COMPBUF_SIZE_CURRENT, in dcn401_init_crb()
562 REG_GET(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_A, in hubbub401_wm_read_state()
565 REG_GET(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_A, in hubbub401_wm_read_state()
568 REG_GET(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_A, in hubbub401_wm_read_state()
571 REG_GET(DCHUBBUB_ARB_UCLK_PSTATE_CHANGE_WATERMARK_A, in hubbub401_wm_read_state()
574 REG_GET(DCHUBBUB_ARB_USR_RETRAINING_WATERMARK_A, in hubbub401_wm_read_state()
[all …]
/linux/drivers/gpu/drm/amd/display/dc/dpp/dcn30/
H A Ddcn30_dpp.c49 REG_GET(DPP_CONTROL, in dpp30_read_state()
58 REG_GET(CM_GAMCOR_CONTROL, in dpp30_read_state()
61 REG_GET(CM_GAMCOR_CONTROL, CM_GAMCOR_SELECT_CURRENT, &gamcor_lut_mode); in dpp30_read_state()
68 REG_GET(CM_SHAPER_CONTROL, CM_SHAPER_LUT_MODE, &s->shaper_lut_mode); in dpp30_read_state()
70 REG_GET(CM_3DLUT_MODE, CM_3DLUT_MODE_CURRENT, &s->lut3d_mode); in dpp30_read_state()
72 REG_GET(CM_3DLUT_READ_WRITE_CONTROL, CM_3DLUT_30BIT_EN, &s->lut3d_bit_depth); in dpp30_read_state()
74 REG_GET(CM_3DLUT_MODE, CM_3DLUT_SIZE, &s->lut3d_size); in dpp30_read_state()
78 REG_GET(CM_BLNDGAM_CONTROL, CM_BLNDGAM_MODE_CURRENT, &s->rgam_lut_mode); in dpp30_read_state()
80 REG_GET(CM_BLNDGAM_CONTROL, CM_BLNDGAM_SELECT_CURRENT, &rgam_lut_mode); in dpp30_read_state()
142 REG_GET(CM_POST_CSC_CONTROL, in dpp3_program_post_csc()
[all …]
H A Ddcn30_dpp_cm.c64 REG_GET(CM_GAMCOR_CONTROL, CM_GAMCOR_MODE_CURRENT, &state_mode); in dpp30_get_gamcor_current()
67 REG_GET(CM_GAMCOR_CONTROL, CM_GAMCOR_SELECT_CURRENT, &lut_mode); in dpp30_get_gamcor_current()
395 REG_GET(CM_GAMUT_REMAP_CONTROL, CM_GAMUT_REMAP_MODE_CURRENT, &gamut_mode); in dpp3_cm_set_gamut_remap()
417 REG_GET(CM_GAMUT_REMAP_CONTROL, CM_GAMUT_REMAP_MODE_CURRENT, &selection); in read_gamut_remap()
/linux/drivers/gpu/drm/amd/display/dc/dwb/dcn30/
H A Ddcn30_dwb.c138 REG_GET(DWB_UPDATE_CTRL, DWB_UPDATE_LOCK, &pre_locked); in dwb3_set_fc_enable()
166 REG_GET(DWB_UPDATE_CTRL, DWB_UPDATE_LOCK, &pre_locked); in dwb3_update()
199 REG_GET(DWB_ENABLE_CLK_CTRL, DWB_ENABLE, &dwb_enabled); in dwb3_is_enabled()
200 REG_GET(FC_MODE_CTRL, FC_FRAME_CAPTURE_EN, &fc_frame_capture_en); in dwb3_is_enabled()
/linux/drivers/gpu/drm/amd/display/dc/dpp/dcn20/
H A Ddcn20_dpp.c56 REG_GET(DPP_CONTROL, in dpp20_read_state()
60 REG_GET(CM_DGAM_CONTROL, in dpp20_read_state()
64 REG_GET(CM_SHAPER_CONTROL, in dpp20_read_state()
69 REG_GET(CM_3DLUT_MODE, in dpp20_read_state()
73 REG_GET(CM_BLNDGAM_LUT_WRITE_EN_MASK, in dpp20_read_state()
/linux/drivers/gpu/drm/amd/display/dc/mpc/dcn20/
H A Ddcn20_mpc.c302 REG_GET(MPCC_OGAM_LUT_RAM_CONTROL[mpcc_id], MPCC_OGAM_CONFIG_STATUS, &state_mode); in mpc20_get_ogam_current()
477 REG_GET(MPCC_STATUS[id], MPCC_DISABLED, &mpc_disabled); in mpc2_assert_idle_mpcc()
491 REG_GET(MPCC_TOP_SEL[mpcc_id], in mpc2_assert_mpcc_idle_before_connect()
550 REG_GET(MPCC_OPP_ID[mpcc_inst], MPCC_OPP_ID, &s->opp_id); in mpc2_read_mpcc_state()
551 REG_GET(MPCC_TOP_SEL[mpcc_inst], MPCC_TOP_SEL, &s->dpp_id); in mpc2_read_mpcc_state()
552 REG_GET(MPCC_BOT_SEL[mpcc_inst], MPCC_BOT_SEL, &s->bot_mpcc_id); in mpc2_read_mpcc_state()
561 REG_GET(MPCC_OGAM_LUT_RAM_CONTROL[mpcc_inst], in mpc2_read_mpcc_state()
/linux/drivers/gpu/drm/omapdrm/dss/
H A Dhdmi4_core.c43 if (REG_GET(base, HDMI_CORE_DDC_STATUS, 4, 4) == 1) { in hdmi4_core_ddc_init()
110 if (REG_GET(base, HDMI_CORE_DDC_STATUS, 6, 6) == 1) { in hdmi4_core_ddc_read()
115 if (REG_GET(base, HDMI_CORE_DDC_STATUS, 5, 5) == 1) { in hdmi4_core_ddc_read()
124 if (REG_GET(base, HDMI_CORE_DDC_STATUS, 4, 4) == 0) { in hdmi4_core_ddc_read()
131 while (REG_GET(base, HDMI_CORE_DDC_STATUS, 2, 2) == 1) { in hdmi4_core_ddc_read()
139 buf[i] = REG_GET(base, HDMI_CORE_DDC_DATA, 7, 0); in hdmi4_core_ddc_read()
H A Dhdmi.h280 #define REG_GET(base, idx, start, end) \ macro
287 while (val != (v = REG_GET(base_addr, idx, b2, b1))) { in hdmi_wait_for_bit_change()
/linux/drivers/video/fbdev/omap2/omapfb/dss/
H A Dhdmi4_core.c44 if (REG_GET(base, HDMI_CORE_DDC_STATUS, 4, 4) == 1) { in hdmi_core_ddc_init()
116 if (REG_GET(base, HDMI_CORE_DDC_STATUS, 6, 6) == 1) { in hdmi_core_ddc_edid()
121 if (REG_GET(base, HDMI_CORE_DDC_STATUS, 5, 5) == 1) { in hdmi_core_ddc_edid()
130 if (REG_GET(base, HDMI_CORE_DDC_STATUS, 4, 4) == 0) { in hdmi_core_ddc_edid()
137 while (REG_GET(base, HDMI_CORE_DDC_STATUS, 2, 2) == 1) { in hdmi_core_ddc_edid()
145 pedid[i] = REG_GET(base, HDMI_CORE_DDC_DATA, 7, 0); in hdmi_core_ddc_edid()
H A Dhdmi.h261 #define REG_GET(base, idx, start, end) \ macro
268 while (val != (v = REG_GET(base_addr, idx, b2, b1))) { in hdmi_wait_for_bit_change()
/linux/drivers/gpu/drm/amd/display/dc/dcn20/
H A Ddcn20_dwb.c177 REG_GET(CNV_UPDATE, CNV_UPDATE_LOCK, &pre_locked); in dwb2_update()
204 REG_GET(WB_ENABLE, WB_ENABLE, &wb_enabled); in dwb2_is_enabled()
205 REG_GET(CNV_MODE, CNV_FRAME_CAPTURE_EN, &cnv_frame_capture_en); in dwb2_is_enabled()
H A Ddcn20_vmid.c61 REG_GET(PAGE_TABLE_BASE_ADDR_LO32, in dcn20_wait_for_vmid_ready()
/linux/drivers/gpu/drm/amd/display/dc/dpp/dcn10/
H A Ddcn10_dpp_cm.c191 REG_GET(CM_GAMUT_REMAP_CONTROL, in read_gamut_remap()
272 REG_GET(CM_TEST_DEBUG_DATA, in dpp1_cm_program_color_matrix()
530 REG_GET(CM_TEST_DEBUG_DATA, in dpp1_program_input_csc()
710 REG_GET(CM_IGAM_LUT_RW_CONTROL, CM_IGAM_DGAM_CONFIG_STATUS, in dpp1_degamma_ram_inuse()
802 REG_GET(CM_IGAM_LUT_RW_CONTROL, CM_IGAM_DGAM_CONFIG_STATUS, in dpp1_ingamma_ram_inuse()
872 REG_GET(CM_IGAM_CONTROL, CM_IGAM_LUT_MODE, &ram_num); in dpp1_program_input_lut()
/linux/drivers/gpu/drm/amd/display/dc/mpc/dcn32/
H A Ddcn32_mpc.c100 REG_GET(MPCC_MCM_1DLUT_CONTROL[mpcc_id], in mpc32_get_post1dlut_current()
102 REG_GET(MPCC_MCM_1DLUT_CONTROL[mpcc_id], in mpc32_get_post1dlut_current()
307 REG_GET(MPCC_MCM_SHAPER_CONTROL[mpcc_id], MPCC_MCM_SHAPER_MODE_CURRENT, &state_mode); in mpc32_get_shaper_current()
701 REG_GET(MPCC_MCM_MEM_PWR_CTRL[mpcc_id], MPCC_MCM_SHAPER_MEM_PWR_STATE, &power_status_shaper); in mpc32_power_on_shaper_3dlut()
702 REG_GET(MPCC_MCM_MEM_PWR_CTRL[mpcc_id], MPCC_MCM_3DLUT_MEM_PWR_STATE, &power_status_3dlut); in mpc32_power_on_shaper_3dlut()
763 REG_GET(MPCC_MCM_3DLUT_MODE[mpcc_id], in get3dlut_config()
766 REG_GET(MPCC_MCM_3DLUT_READ_WRITE_CONTROL[mpcc_id], in get3dlut_config()
788 REG_GET(MPCC_MCM_3DLUT_MODE[mpcc_id], MPCC_MCM_3DLUT_SIZE, &lut_size); in get3dlut_config()
/linux/drivers/gpu/drm/amd/display/dc/hubbub/dcn20/
H A Ddcn20_hubbub.c641 REG_GET(DCN_VM_FAULT_CNTL, DCN_VM_ERROR_STATUS_MODE, &hubbub_state->vm_error_mode); in hubbub2_read_state()
644 REG_GET(DCN_VM_FAULT_STATUS, DCN_VM_ERROR_STATUS, &hubbub_state->vm_error_status); in hubbub2_read_state()
645 REG_GET(DCN_VM_FAULT_STATUS, DCN_VM_ERROR_VMID, &hubbub_state->vm_error_vmid); in hubbub2_read_state()
646 REG_GET(DCN_VM_FAULT_STATUS, DCN_VM_ERROR_PIPE, &hubbub_state->vm_error_pipe); in hubbub2_read_state()
/linux/drivers/gpu/drm/amd/display/dc/dcn31/
H A Ddcn31_vpg.c68 REG_GET(VPG_MEM_PWR, VPG_GSP_MEM_PWR_STATE, &vpg_gsp_mem_pwr_state); in vpg31_poweron()

123