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Searched refs:REGS (Results 1 – 25 of 32) sorted by relevance

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/linux/arch/hexagon/include/asm/
H A Delf.h91 #define CS_COPYREGS(DEST,REGS) \ argument
93 DEST.cs0 = REGS->cs0;\
94 DEST.cs1 = REGS->cs1;\
97 #define CS_COPYREGS(DEST,REGS) argument
100 #define ELF_CORE_COPY_REGS(DEST, REGS) \ argument
102 DEST.r0 = REGS->r00; \
103 DEST.r1 = REGS->r01; \
104 DEST.r2 = REGS->r02; \
105 DEST.r3 = REGS->r03; \
106 DEST.r4 = REGS->r04; \
[all …]
/linux/arch/arm/probes/
H A Ddecode-arm.c156 REGS(0, NOPC, 0, 0, 0)),
163 REGS(0, 0, 0, 0, NOPC)),
167 REGS(0, NOPC, 0, 0, NOPC)),
174 REGS(NOPC, NOPC, 0, 0, NOPC)),
190 REGS(NOPC, NOPC, NOPC, 0, NOPC)),
196 REGS(NOPC, 0, NOPC, 0, NOPC)),
202 REGS(NOPC, NOPC, NOPC, 0, NOPC)),
213 REGS(NOPC, 0, NOPC, 0, NOPC)),
220 REGS(NOPC, NOPC, NOPC, 0, NOPC)),
233 REGS(NOPC, NOPC, NOPC, 0, NOPC)),
[all …]
H A Ddecode-thumb.c54 REGS(NOPCWB, NOSPPC, NOSPPC, 0, 0)),
59 REGS(NOSP, 0, 0, 0, NOSPPC)),
79 REGS(NOSPPC, 0, 0, 0, NOSPPC)),
85 REGS(NOPC, 0, 0, 0, NOSPPC)),
90 REGS(0, 0, NOSPPC, 0, NOSPPC)),
105 REGS(SP, 0, SP, 0, NOSPPC)),
114 REGS(SP, 0, NOPC, 0, NOSPPC)),
128 REGS(NOSPPC, 0, NOSPPC, 0, NOSPPC)),
139 REGS(NOSPPC, 0, 0, 0, 0)),
145 REGS(NOPC, 0, 0, 0, 0)),
[all …]
H A Ddecode.h263 #define REGS(r16, r12, r8, r4, r0) \ macro
/linux/drivers/media/i2c/
H A Dar0521.c672 #define REGS(...) REGS_ENTRY(((const __be16[]){__VA_ARGS__})) macro
678 REGS(be(0x0112), be(0x0808)), /* 8-bit/8-bit mode */
681 REGS(be(0x301E), be(0x00AA)),
684 REGS(be(0x3042),
688 REGS(be(0x30D2),
694 REGS(be(0x30DA),
700 REGS(be(0x30EE), be(0x1136)),
701 REGS(be(0x30FA), be(0xFD00)), /* GPIO0 = flash, GPIO1 = shutter */
702 REGS(be(0x3120), be(0x0005)), /* p1 dither enabled for 10bit mode */
703 REGS(be(0x3172), be(0x0206)), /* txlo clk divider options */
[all …]
H A Dimx258.c531 #define REGS(_list) { .num_of_regs = ARRAY_SIZE(_list), .regs = _list, } macro
540 .reg_list = REGS(mipi_1267mbps_19_2mhz_2l),
544 .reg_list = REGS(mipi_1267mbps_19_2mhz_4l),
553 .reg_list = REGS(mipi_640mbps_19_2mhz_2l),
557 .reg_list = REGS(mipi_640mbps_19_2mhz_4l),
569 .reg_list = REGS(mipi_1272mbps_24mhz_2l),
573 .reg_list = REGS(mipi_1272mbps_24mhz_4l),
582 .reg_list = REGS(mipi_642mbps_24mhz_2l),
586 .reg_list = REGS(mipi_642mbps_24mhz_4l),
/linux/drivers/video/fbdev/nvidia/
H A Dnv_setup.c295 par->PRAMIN = par->REGS + (0x00710000 / 4); in NVCommonSetup()
296 par->PCRTC0 = par->REGS + (0x00600000 / 4); in NVCommonSetup()
297 par->PRAMDAC0 = par->REGS + (0x00680000 / 4); in NVCommonSetup()
298 par->PFB = par->REGS + (0x00100000 / 4); in NVCommonSetup()
299 par->PFIFO = par->REGS + (0x00002000 / 4); in NVCommonSetup()
300 par->PGRAPH = par->REGS + (0x00400000 / 4); in NVCommonSetup()
301 par->PEXTDEV = par->REGS + (0x00101000 / 4); in NVCommonSetup()
302 par->PTIMER = par->REGS + (0x00009000 / 4); in NVCommonSetup()
303 par->PMC = par->REGS + (0x00000000 / 4); in NVCommonSetup()
304 par->FIFO = par->REGS + (0x00800000 / 4); in NVCommonSetup()
[all …]
H A Dnvidia.c1205 volatile u32 __iomem *REGS) in nvidia_get_chipset() argument
1214 id = NV_RD32(REGS, 0x1800); in nvidia_get_chipset()
1284 volatile u32 __iomem *REGS; in nvidiafb_probe() local
1304 REGS = ioremap(nvidiafb_fix.mmio_start, nvidiafb_fix.mmio_len); in nvidiafb_probe()
1305 if (!REGS) { in nvidiafb_probe()
1310 Chipset = nvidia_get_chipset(pd, REGS); in nvidiafb_probe()
1349 par->REGS = REGS; in nvidiafb_probe()
1433 iounmap(REGS); in nvidiafb_probe()
1451 iounmap(par->REGS); in nvidiafb_remove()
H A Dnv_type.h155 volatile u32 __iomem *REGS; member
/linux/drivers/gpu/drm/msm/adreno/
H A Da6xx_gpu_state.h299 #define REGS(_array, _sel_reg, _sel_val) \ macro
304 REGS(a6xx_registers, 0, 0),
305 REGS(a660_registers, 0, 0),
306 REGS(a6xx_rb_rac_registers, REG_A6XX_RB_RB_SUB_BLOCK_SEL_CNTL_CD, 0),
307 REGS(a6xx_rb_rbp_registers, REG_A6XX_RB_RB_SUB_BLOCK_SEL_CNTL_CD, 9),
336 REGS(a6xx_ahb_registers, 0, 0);
339 REGS(a6xx_vbif_registers, 0, 0);
342 REGS(a6xx_gbif_registers, 0, 0);
384 REGS(a6xx_gmu_cx_registers, 0, 0),
385 REGS(a6xx_gmu_cx_rscc_registers, 0, 0),
[all …]
/linux/drivers/gpu/drm/amd/display/dmub/src/
H A Ddmub_reg.h43 #define REG(reg) (REGS)->offset.reg
45 #define FD(reg_field) (REGS)->shift.reg_field, (REGS)->mask.reg_field
H A Ddmub_dcn301.c36 #define REGS dmub->regs macro
H A Ddmub_dcn303.c37 #define REGS dmub->regs macro
H A Ddmub_dcn21.c36 #define REGS dmub->regs macro
H A Ddmub_dcn302.c36 #define REGS dmub->regs macro
H A Ddmub_dcn316.c42 #define REGS dmub->regs_dcn31 macro
H A Ddmub_dcn315.c42 #define REGS dmub->regs_dcn31 macro
H A Ddmub_dcn314.c42 #define REGS dmub->regs_dcn31 macro
H A Ddmub_dcn351.c13 #define REGS dmub->regs_dcn35 macro
H A Ddmub_dcn30.c37 #define REGS dmub->regs macro
H A Ddmub_dcn20.c37 #define REGS dmub->regs macro
H A Ddmub_dcn31.c36 #define REGS dmub->regs_dcn31 macro
H A Ddmub_dcn32.c37 #define REGS dmub->regs_dcn32 macro
/linux/arch/alpha/include/asm/
H A Delf.h114 #define ELF_CORE_COPY_REGS(DEST, REGS) \ argument
115 dump_elf_thread(DEST, REGS, current_thread_info());
/linux/drivers/gpu/drm/amd/amdgpu/
H A Duvd_v3_1.c211 WREG32_FIELD(UVD_CGC_GATE, REGS, 0); in uvd_v3_1_set_dcm()

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