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Searched refs:RB_BLKSZ (Results 1 – 12 of 12) sorted by relevance

/linux/drivers/gpu/drm/amd/amdgpu/
H A Dvcn_v3_0.c1140 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_BLKSZ, 1); in vcn_v3_0_start_dpg_mode()
1331 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_BLKSZ, 1); in vcn_v3_0_start()
1521 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_BLKSZ, 1); in vcn_v3_0_start_sriov()
H A Dgfx_v11_0.c3734 tmp = REG_SET_FIELD(tmp, CP_RB0_CNTL, RB_BLKSZ, rb_bufsz - 2); in gfx_v11_0_cp_gfx_resume()
3774 tmp = REG_SET_FIELD(tmp, CP_RB1_CNTL, RB_BLKSZ, rb_bufsz - 2); in gfx_v11_0_cp_gfx_resume()
4142 tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_CNTL, RB_BLKSZ, rb_bufsz - 2); in gfx_v11_0_gfx_mqd_init()
H A Dgfx_v12_0.c2730 tmp = REG_SET_FIELD(tmp, CP_RB0_CNTL, RB_BLKSZ, rb_bufsz - 2); in gfx_v12_0_cp_gfx_resume()
3022 tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_CNTL, RB_BLKSZ, rb_bufsz - 2); in gfx_v12_0_gfx_mqd_init()
H A Dgfx_v10_0.c6520 tmp = REG_SET_FIELD(tmp, CP_RB0_CNTL, RB_BLKSZ, rb_bufsz - 2); in gfx_v10_0_cp_gfx_resume()
6563 tmp = REG_SET_FIELD(tmp, CP_RB1_CNTL, RB_BLKSZ, rb_bufsz - 2); in gfx_v10_0_cp_gfx_resume()
6818 tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_CNTL, RB_BLKSZ, rb_bufsz - 2); in gfx_v10_0_gfx_mqd_init()
/linux/drivers/gpu/drm/radeon/
H A Drv770d.h351 #define RB_BLKSZ(x) ((x) << 8) macro
H A Dnid.h486 #define RB_BLKSZ(x) ((x) << 8) macro
H A Dcikd.h1304 #define RB_BLKSZ(x) ((x) << 8) macro
H A Drv770.c1102 RB_NO_UPDATE | RB_BLKSZ(15) | RB_BUFSZ(3)); in rv770_cp_load_microcode()
H A Devergreend.h478 #define RB_BLKSZ(x) ((x) << 8) macro
H A Dr600d.h197 #define RB_BLKSZ(x) ((x) << 8) macro
H A Dr600.c2658 RB_NO_UPDATE | RB_BLKSZ(15) | RB_BUFSZ(3)); in r600_cp_load_microcode()
H A Devergreen.c2977 RB_NO_UPDATE | RB_BLKSZ(15) | RB_BUFSZ(3)); in evergreen_cp_load_microcode()