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Searched refs:PP_ASSERT_WITH_CODE (Results 1 – 17 of 17) sorted by relevance

/linux/drivers/gpu/drm/amd/pm/powerplay/smumgr/
H A Dvega20_smumgr.c171 PP_ASSERT_WITH_CODE(table_id < TABLE_COUNT, in vega20_copy_table_from_smc()
173 PP_ASSERT_WITH_CODE(priv->smu_tables.entry[table_id].version != 0, in vega20_copy_table_from_smc()
175 PP_ASSERT_WITH_CODE(priv->smu_tables.entry[table_id].size != 0, in vega20_copy_table_from_smc()
178 PP_ASSERT_WITH_CODE((ret = smum_send_msg_to_smc_with_parameter(hwmgr, in vega20_copy_table_from_smc()
184 PP_ASSERT_WITH_CODE((ret = smum_send_msg_to_smc_with_parameter(hwmgr, in vega20_copy_table_from_smc()
190 PP_ASSERT_WITH_CODE((ret = smum_send_msg_to_smc_with_parameter(hwmgr, in vega20_copy_table_from_smc()
216 PP_ASSERT_WITH_CODE(table_id < TABLE_COUNT, in vega20_copy_table_to_smc()
218 PP_ASSERT_WITH_CODE(priv->smu_tables.entry[table_id].version != 0, in vega20_copy_table_to_smc()
220 PP_ASSERT_WITH_CODE(priv->smu_tables.entry[table_id].size != 0, in vega20_copy_table_to_smc()
228 PP_ASSERT_WITH_CODE((ret = smum_send_msg_to_smc_with_parameter(hwmgr, in vega20_copy_table_to_smc()
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H A Dvega12_smumgr.c47 PP_ASSERT_WITH_CODE(table_id < TABLE_COUNT, in vega12_copy_table_from_smc()
49 PP_ASSERT_WITH_CODE(priv->smu_tables.entry[table_id].version != 0, in vega12_copy_table_from_smc()
51 PP_ASSERT_WITH_CODE(priv->smu_tables.entry[table_id].size != 0, in vega12_copy_table_from_smc()
53 PP_ASSERT_WITH_CODE(smum_send_msg_to_smc_with_parameter(hwmgr, in vega12_copy_table_from_smc()
58 PP_ASSERT_WITH_CODE(smum_send_msg_to_smc_with_parameter(hwmgr, in vega12_copy_table_from_smc()
64 PP_ASSERT_WITH_CODE(smum_send_msg_to_smc_with_parameter(hwmgr, in vega12_copy_table_from_smc()
91 PP_ASSERT_WITH_CODE(table_id < TABLE_COUNT, in vega12_copy_table_to_smc()
93 PP_ASSERT_WITH_CODE(priv->smu_tables.entry[table_id].version != 0, in vega12_copy_table_to_smc()
95 PP_ASSERT_WITH_CODE(priv->smu_tables.entry[table_id].size != 0, in vega12_copy_table_to_smc()
103 PP_ASSERT_WITH_CODE(smum_send_msg_to_smc_with_parameter(hwmgr, in vega12_copy_table_to_smc()
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H A Diceland_smumgr.c164 …PP_ASSERT_WITH_CODE((limit >= byte_count), "SMC address is beyond the SMC RAM area.", return -EINV… in iceland_upload_smc_firmware_data()
178 PP_ASSERT_WITH_CODE((0 == byte_count), "SMC size must be divisible by 4.", return -EINVAL); in iceland_upload_smc_firmware_data()
345 PP_ASSERT_WITH_CODE(false, in iceland_populate_dw8()
396 PP_ASSERT_WITH_CODE(NULL != hwmgr->dyn_state.cac_leakage_table, in iceland_populate_bapm_vddc_vid_sidd()
398 PP_ASSERT_WITH_CODE(hwmgr->dyn_state.cac_leakage_table->count <= 8, in iceland_populate_bapm_vddc_vid_sidd()
400 …PP_ASSERT_WITH_CODE(hwmgr->dyn_state.cac_leakage_table->count == hwmgr->dyn_state.vddc_dependency_… in iceland_populate_bapm_vddc_vid_sidd()
409 PP_ASSERT_WITH_CODE(false, "Iceland should always support EVV", return -EINVAL); in iceland_populate_bapm_vddc_vid_sidd()
422 PP_ASSERT_WITH_CODE(data->vddc_voltage_table.count <= 8, in iceland_populate_vddc_vid()
446 PP_ASSERT_WITH_CODE(false, in iceland_populate_pm_fuses()
452 PP_ASSERT_WITH_CODE(false, in iceland_populate_pm_fuses()
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H A Dvegam_smumgr.c139 PP_ASSERT_WITH_CODE(false, "SMU Firmware start failed!", return -1); in vegam_start_smu_in_protection_mode()
211 PP_ASSERT_WITH_CODE(0, "Failed to load SMU ucode.", return result); in vegam_start_smu()
797 PP_ASSERT_WITH_CODE((clock >= min), in vegam_get_sleep_divider_id_from_clock()
827 PP_ASSERT_WITH_CODE((0 == result), in vegam_populate_single_graphic_level()
918 PP_ASSERT_WITH_CODE((1 <= pcie_entry_cnt), in vegam_populate_all_graphic_levels()
968 PP_ASSERT_WITH_CODE(!atomctrl_get_memory_pll_dividers_ai(hwmgr, in vegam_calculate_mclk_params()
995 PP_ASSERT_WITH_CODE(!result, in vegam_populate_single_memory_level()
1001 PP_ASSERT_WITH_CODE(!result, in vegam_populate_single_memory_level()
1050 PP_ASSERT_WITH_CODE((0 != dpm_table->mclk_table.dpm_levels[i].value), in vegam_populate_all_memory_levels()
1101 PP_ASSERT_WITH_CODE(i < table_info->vdd_dep_on_mclk->count, in vegam_populate_mvdd_value()
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H A Dfiji_smumgr.c149 PP_ASSERT_WITH_CODE(false, in fiji_start_smu_in_protection_mode()
229 PP_ASSERT_WITH_CODE(0 == smu7_read_smc_sram_dword(hwmgr, in fiji_setup_graphics_level_structure()
244 PP_ASSERT_WITH_CODE(0 == smu7_copy_bytes_to_smc(hwmgr, vr_config_addr, in fiji_setup_graphics_level_structure()
252 PP_ASSERT_WITH_CODE(0 == smu7_copy_bytes_to_smc(hwmgr, level_addr, in fiji_setup_graphics_level_structure()
265 PP_ASSERT_WITH_CODE(0 == fiji_setup_graphics_level_structure(hwmgr), in fiji_avfs_event_mgr()
269 PP_ASSERT_WITH_CODE(0 == smu7_setup_pwr_virus(hwmgr), in fiji_avfs_event_mgr()
273 PP_ASSERT_WITH_CODE(0 == fiji_start_avfs_btc(hwmgr), in fiji_avfs_event_mgr()
507 PP_ASSERT_WITH_CODE(cac_dtp_table->usTargetOperatingTemp <= 255, in fiji_populate_bapm_parameters_in_dpm_table()
613 PP_ASSERT_WITH_CODE(false, in fiji_populate_dw8()
700 PP_ASSERT_WITH_CODE(false, in fiji_populate_pm_fuses()
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H A Dpolaris10_smumgr.c131 PP_ASSERT_WITH_CODE(0 == smu7_read_smc_sram_dword(hwmgr, in polaris10_setup_graphics_level_structure()
142 PP_ASSERT_WITH_CODE(0 == smu7_copy_bytes_to_smc(hwmgr, vr_config_address, in polaris10_setup_graphics_level_structure()
149 PP_ASSERT_WITH_CODE(0 == smu7_copy_bytes_to_smc(hwmgr, graphics_level_address, in polaris10_setup_graphics_level_structure()
157 PP_ASSERT_WITH_CODE(0 == smu7_copy_bytes_to_smc(hwmgr, graphics_level_address, in polaris10_setup_graphics_level_structure()
166 PP_ASSERT_WITH_CODE(0 == smu7_copy_bytes_to_smc(hwmgr, graphics_level_address, in polaris10_setup_graphics_level_structure()
182 PP_ASSERT_WITH_CODE(0 == polaris10_setup_graphics_level_structure(hwmgr), in polaris10_avfs_event_mgr()
188 PP_ASSERT_WITH_CODE(0 == smu7_setup_pwr_virus(hwmgr), in polaris10_avfs_event_mgr()
193 PP_ASSERT_WITH_CODE(0 == polaris10_perform_btc(hwmgr), in polaris10_avfs_event_mgr()
239 PP_ASSERT_WITH_CODE(false, "SMU Firmware start failed!", return -1); in polaris10_start_smu_in_protection_mode()
309 PP_ASSERT_WITH_CODE(0, "Failed to load SMU ucode.", return result); in polaris10_start_smu()
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H A Dtonga_smumgr.c452 PP_ASSERT_WITH_CODE(!result, in tonga_populate_smc_voltage_tables()
457 PP_ASSERT_WITH_CODE(!result, in tonga_populate_smc_voltage_tables()
462 PP_ASSERT_WITH_CODE(!result, in tonga_populate_smc_voltage_tables()
467 PP_ASSERT_WITH_CODE(!result, in tonga_populate_smc_voltage_tables()
472 PP_ASSERT_WITH_CODE(!result, in tonga_populate_smc_voltage_tables()
556 PP_ASSERT_WITH_CODE(result == 0, in tonga_calculate_sclk_params()
638 PP_ASSERT_WITH_CODE((!result), in tonga_populate_single_graphic_level()
736 PP_ASSERT_WITH_CODE((pcie_entry_count >= 1), in tonga_populate_all_graphic_levels()
812 PP_ASSERT_WITH_CODE( in tonga_calculate_mclk_params()
987 PP_ASSERT_WITH_CODE( in tonga_populate_single_memory_level()
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H A Dci_smumgr.c315 PP_ASSERT_WITH_CODE(result == 0, in ci_calculate_sclk_params()
551 PP_ASSERT_WITH_CODE(false, in ci_populate_dw8()
584 PP_ASSERT_WITH_CODE(NULL != hwmgr->dyn_state.cac_leakage_table, in ci_populate_bapm_vddc_vid_sidd()
586 PP_ASSERT_WITH_CODE(hwmgr->dyn_state.cac_leakage_table->count <= 8, in ci_populate_bapm_vddc_vid_sidd()
588 …PP_ASSERT_WITH_CODE(hwmgr->dyn_state.cac_leakage_table->count == hwmgr->dyn_state.vddc_dependency_… in ci_populate_bapm_vddc_vid_sidd()
612 PP_ASSERT_WITH_CODE(data->vddc_voltage_table.count <= 8, in ci_populate_vddc_vid()
772 PP_ASSERT_WITH_CODE(NULL != hwmgr->dyn_state.vddc_dependency_on_sclk, in ci_get_std_voltage_value_sidd()
852 PP_ASSERT_WITH_CODE(0 == result, "do not populate SMC VDDC voltage table", return -EINVAL); in ci_populate_smc_vddc_table()
882 PP_ASSERT_WITH_CODE(result == 0, "do not populate SMC VDDCI voltage table", return -EINVAL); in ci_populate_smc_vdd_ci_table()
910 PP_ASSERT_WITH_CODE(result == 0, "do not populate SMC mvdd voltage table", return -EINVAL); in ci_populate_smc_mvdd_table()
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H A Dvega10_smumgr.c44 PP_ASSERT_WITH_CODE(table_id < MAX_SMU_TABLE, in vega10_copy_table_from_smc()
46 PP_ASSERT_WITH_CODE(priv->smu_tables.entry[table_id].version != 0, in vega10_copy_table_from_smc()
48 PP_ASSERT_WITH_CODE(priv->smu_tables.entry[table_id].size != 0, in vega10_copy_table_from_smc()
83 PP_ASSERT_WITH_CODE(table_id < MAX_SMU_TABLE, in vega10_copy_table_to_smc()
85 PP_ASSERT_WITH_CODE(priv->smu_tables.entry[table_id].version != 0, in vega10_copy_table_to_smc()
87 PP_ASSERT_WITH_CODE(priv->smu_tables.entry[table_id].size != 0, in vega10_copy_table_to_smc()
185 PP_ASSERT_WITH_CODE(!smum_send_msg_to_smc(hwmgr, in vega10_verify_smc_interface()
364 PP_ASSERT_WITH_CODE(!vega10_verify_smc_interface(hwmgr), in vega10_start_smu()
H A Dsmu10_smumgr.c123 PP_ASSERT_WITH_CODE(table_id < MAX_SMU_TABLE, in smu10_copy_table_from_smc()
125 PP_ASSERT_WITH_CODE(priv->smu_tables.entry[table_id].version != 0, in smu10_copy_table_from_smc()
127 PP_ASSERT_WITH_CODE(priv->smu_tables.entry[table_id].size != 0, in smu10_copy_table_from_smc()
157 PP_ASSERT_WITH_CODE(table_id < MAX_SMU_TABLE, in smu10_copy_table_to_smc()
159 PP_ASSERT_WITH_CODE(priv->smu_tables.entry[table_id].version != 0, in smu10_copy_table_to_smc()
161 PP_ASSERT_WITH_CODE(priv->smu_tables.entry[table_id].size != 0, in smu10_copy_table_to_smc()
/linux/drivers/gpu/drm/amd/pm/powerplay/hwmgr/
H A Dvega12_hwmgr.c472 PP_ASSERT_WITH_CODE(!vega12_init_sclk_threshold(hwmgr), in vega12_setup_asic_task()
542 PP_ASSERT_WITH_CODE(!ret, in vega12_override_pcie_parameters()
559 PP_ASSERT_WITH_CODE(!ret, in vega12_override_pcie_parameters()
569 PP_ASSERT_WITH_CODE(!ret, in vega12_override_pcie_parameters()
587 PP_ASSERT_WITH_CODE(!ret, in vega12_get_number_of_dpm_level()
601 PP_ASSERT_WITH_CODE(smum_send_msg_to_smc_with_parameter(hwmgr, in vega12_get_dpm_frequency_by_index()
617 PP_ASSERT_WITH_CODE(!ret, in vega12_setup_single_dpm_table()
625 PP_ASSERT_WITH_CODE(!ret, in vega12_setup_single_dpm_table()
657 PP_ASSERT_WITH_CODE(!ret, in vega12_setup_default_dpm_tables()
670 PP_ASSERT_WITH_CODE(!ret, in vega12_setup_default_dpm_tables()
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H A Dvega20_hwmgr.c508 PP_ASSERT_WITH_CODE(!ret, in vega20_setup_asic_task()
545 PP_ASSERT_WITH_CODE(!ret, in vega20_get_number_of_dpm_level()
561 PP_ASSERT_WITH_CODE(!ret, in vega20_get_dpm_frequency_by_index()
575 PP_ASSERT_WITH_CODE(!ret, in vega20_setup_single_dpm_table()
583 PP_ASSERT_WITH_CODE(!ret, in vega20_setup_single_dpm_table()
603 PP_ASSERT_WITH_CODE(!ret, in vega20_setup_gfxclk_dpm_table()
624 PP_ASSERT_WITH_CODE(!ret, in vega20_setup_memclk_dpm_table()
656 PP_ASSERT_WITH_CODE(!ret, in vega20_setup_default_dpm_tables()
683 PP_ASSERT_WITH_CODE(!ret, in vega20_setup_default_dpm_tables()
696 PP_ASSERT_WITH_CODE(!ret, in vega20_setup_default_dpm_tables()
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H A Dsmu7_hwmgr.c180 PP_ASSERT_WITH_CODE((PhwVIslands_Magic == hw_ps->magic), in cast_phw_smu7_power_state()
190 PP_ASSERT_WITH_CODE((PhwVIslands_Magic == hw_ps->magic), in cast_const_phw_smu7_power_state()
231 PP_ASSERT_WITH_CODE((7 >= link_width), in smu7_get_current_pcie_lane_number()
293 PP_ASSERT_WITH_CODE((NULL != voltage_table), in phm_get_svi2_voltage_table_v0()
328 PP_ASSERT_WITH_CODE((0 == result), in smu7_construct_voltage_tables()
339 PP_ASSERT_WITH_CODE((0 == result), in smu7_construct_voltage_tables()
348 PP_ASSERT_WITH_CODE((0 == result), in smu7_construct_voltage_tables()
358 PP_ASSERT_WITH_CODE((0 == result), in smu7_construct_voltage_tables()
367 PP_ASSERT_WITH_CODE((0 == result), in smu7_construct_voltage_tables()
376 PP_ASSERT_WITH_CODE((0 == result), in smu7_construct_voltage_tables()
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H A Dvega12_thermal.c34 PP_ASSERT_WITH_CODE(!smum_send_msg_to_smc(hwmgr, in vega12_get_current_rpm()
74 PP_ASSERT_WITH_CODE(!vega12_enable_smc_features( in vega12_enable_fan_control_feature()
92 PP_ASSERT_WITH_CODE(!vega12_enable_smc_features( in vega12_disable_fan_control_feature()
109 PP_ASSERT_WITH_CODE( in vega12_fan_ctrl_start_smc_fan_control()
123 PP_ASSERT_WITH_CODE(!vega12_disable_fan_control_feature(hwmgr), in vega12_fan_ctrl_stop_smc_fan_control()
H A Dvega10_powertune.c753 …PP_ASSERT_WITH_CODE((config_regs != NULL), "[vega10_program_didt_config_registers] Invalid config … in vega10_program_didt_config_registers()
1138 …PP_ASSERT_WITH_CODE((0 == result), "[DisableDiDtConfig] Pre DIDT disable clock gating failed!", re… in vega10_disable_se_edc_force_stall_config()
1155 …PP_ASSERT_WITH_CODE((0 == result), "[EnableDiDt] Attempt to enable DiDt Mode 0 Failed!", return re… in vega10_enable_didt_config()
1159 …PP_ASSERT_WITH_CODE((0 == result), "[EnableDiDt] Attempt to enable DiDt Mode 2 Failed!", return re… in vega10_enable_didt_config()
1163 …PP_ASSERT_WITH_CODE((0 == result), "[EnableDiDt] Attempt to enable DiDt Mode 3 Failed!", return re… in vega10_enable_didt_config()
1169 …PP_ASSERT_WITH_CODE((0 == result), "[EnableDiDt] Attempt to enable DiDt Mode 5 Failed!", return re… in vega10_enable_didt_config()
1173 …PP_ASSERT_WITH_CODE((0 == result), "[EnableDiDt] Attempt to enable DiDt Mode 6 Failed!", return re… in vega10_enable_didt_config()
1182 …PP_ASSERT_WITH_CODE((0 == result), "[EnableDiDtConfig] Attempt to Enable DiDt feature Failed!", re… in vega10_enable_didt_config()
1202 …PP_ASSERT_WITH_CODE((0 == result), "[DisableDiDt] Attempt to disable DiDt Mode 0 Failed!", return … in vega10_disable_didt_config()
1206 …PP_ASSERT_WITH_CODE((0 == result), "[DisableDiDt] Attempt to disable DiDt Mode 2 Failed!", return … in vega10_disable_didt_config()
[all …]
H A Dsmu7_powertune.c904 PP_ASSERT_WITH_CODE((config_regs != NULL), "Invalid config register table.", return -EINVAL); in smu7_program_pt_config_registers()
985 PP_ASSERT_WITH_CODE((result == 0), "DIDT Config failed.", goto error); in smu7_enable_didt_config()
987 PP_ASSERT_WITH_CODE((result == 0), "DIDT Config failed.", goto error); in smu7_enable_didt_config()
990 PP_ASSERT_WITH_CODE((result == 0), "DIDT Config failed.", goto error); in smu7_enable_didt_config()
997 PP_ASSERT_WITH_CODE((result == 0), "DIDT Config failed.", goto error); in smu7_enable_didt_config()
1000 PP_ASSERT_WITH_CODE((result == 0), "DIDT Config failed.", goto error); in smu7_enable_didt_config()
1002 PP_ASSERT_WITH_CODE((result == 0), "DIDT Config failed.", goto error); in smu7_enable_didt_config()
1005 PP_ASSERT_WITH_CODE((result == 0), "DIDT Config failed.", goto error); in smu7_enable_didt_config()
1007 PP_ASSERT_WITH_CODE((result == 0), "DIDT Config failed.", goto error); in smu7_enable_didt_config()
1013 PP_ASSERT_WITH_CODE((result == 0), "EnableDiDt failed.", goto error); in smu7_enable_didt_config()
[all …]
/linux/drivers/gpu/drm/amd/pm/powerplay/inc/
H A Dpp_debug.h37 #define PP_ASSERT_WITH_CODE(cond, msg, code) \ macro