| /linux/include/dt-bindings/clock/ |
| H A D | samsung,s3c64xx-clock.h | 68 #define PCLK_SPI0 53 macro
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| H A D | exynos7-clk.h | 104 #define PCLK_SPI0 12 macro
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| H A D | rk3128-cru.h | 107 #define PCLK_SPI0 338 macro
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| H A D | rk3228-cru.h | 106 #define PCLK_SPI0 338 macro
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| H A D | rockchip,rk3506-cru.h | 134 #define PCLK_SPI0 121 macro
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| H A D | rk3308-cru.h | 186 #define PCLK_SPI0 207 macro
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| H A D | px30-cru.h | 164 #define PCLK_SPI0 341 macro
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| H A D | rk3288-cru.h | 130 #define PCLK_SPI0 338 macro
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| H A D | rk3368-cru.h | 123 #define PCLK_SPI0 338 macro
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| H A D | rockchip,rv1126b-cru.h | 305 #define PCLK_SPI0 292 macro
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| H A D | rockchip,rk3528-cru.h | 237 #define PCLK_SPI0 225 macro
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| H A D | rockchip,rv1126-cru.h | 50 #define PCLK_SPI0 37 macro
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| H A D | rockchip,rk3576-cru.h | 169 #define PCLK_SPI0 151 macro
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| H A D | rk3399-cru.h | 242 #define PCLK_SPI0 347 macro
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| H A D | rockchip,rk3588-cru.h | 161 #define PCLK_SPI0 146 macro
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| H A D | rk3568-cru.h | 401 #define PCLK_SPI0 337 macro
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| /linux/drivers/clk/rockchip/ |
| H A D | clk-rk3128.c | 501 GATE(PCLK_SPI0, "pclk_spi0", "pclk_peri", 0, RK2928_CLKGATE_CON(7), 12, GFLAGS),
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| H A D | clk-rk3228.c | 607 GATE(PCLK_SPI0, "pclk_spi0", "pclk_cpu", 0, RK2928_CLKGATE_CON(9), 6, GFLAGS),
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| H A D | clk-rk3368.c | 802 GATE(PCLK_SPI0, "pclk_spi0", "pclk_peri", 0, RK3368_CLKGATE_CON(19), 4, GFLAGS),
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| H A D | clk-rk3506.c | 463 GATE(PCLK_SPI0, "pclk_spi0", "pclk_lsperi_root", 0,
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| H A D | clk-rk3288.c | 735 GATE(PCLK_SPI0, "pclk_spi0", "pclk_peri", 0, RK3288_CLKGATE_CON(6), 4, GFLAGS),
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| H A D | clk-rk3308.c | 875 GATE(PCLK_SPI0, "pclk_spi0", "pclk_bus", 0, RK3308_CLKGATE_CON(6), 4, GFLAGS),
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| H A D | clk-px30.c | 858 GATE(PCLK_SPI0, "pclk_spi0", "pclk_bus_pre", 0, PX30_CLKGATE_CON(15), 1, GFLAGS),
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| H A D | clk-rv1126.c | 331 GATE(PCLK_SPI0, "pclk_spi0", "pclk_pdpmu", 0,
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| /linux/arch/arm/boot/dts/rockchip/ |
| H A D | rk3xxx.dtsi | 454 clocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>;
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