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Searched refs:PACKET3 (Results 1 – 23 of 23) sorted by relevance

/linux/drivers/gpu/drm/amd/amdgpu/
H A Dgfx_v6_0.c1867 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1)); in gfx_v6_0_ring_test_ring()
1886 amdgpu_ring_write(ring, PACKET3(PACKET3_EVENT_WRITE, 0)); in gfx_v6_0_ring_emit_vgt_flush()
1897 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1)); in gfx_v6_0_ring_emit_fence()
1900 amdgpu_ring_write(ring, PACKET3(PACKET3_SURFACE_SYNC, 3)); in gfx_v6_0_ring_emit_fence()
1909 amdgpu_ring_write(ring, PACKET3(PACKET3_EVENT_WRITE_EOP, 4)); in gfx_v6_0_ring_emit_fence()
1929 amdgpu_ring_write(ring, PACKET3(PACKET3_SWITCH_BUFFER, 0)); in gfx_v6_0_ring_emit_ib()
1934 header = PACKET3(PACKET3_INDIRECT_BUFFER_CONST, 2); in gfx_v6_0_ring_emit_ib()
1936 header = PACKET3(PACKET3_INDIRECT_BUFFER, 2); in gfx_v6_0_ring_emit_ib()
1974 ib.ptr[0] = PACKET3(PACKET3_SET_CONFIG_REG, 1); in gfx_v6_0_ring_test_ib()
2082 amdgpu_ring_write(ring, PACKET3(PACKET3_ME_INITIALIZE, 5)); in gfx_v6_0_cp_gfx_start()
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H A Dgfx_v9_0.c936 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_SET_RESOURCES, 6)); in gfx_v9_0_kiq_set_resources()
958 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_MAP_QUEUES, 5)); in gfx_v9_0_kiq_map_queues()
988 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_UNMAP_QUEUES, 4)); in gfx_v9_0_kiq_unmap_queues()
1016 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_QUERY_STATUS, 5)); in gfx_v9_0_kiq_query_status()
1035 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_INVALIDATE_TLBS, 0)); in gfx_v9_0_kiq_invalidate_tlbs()
1163 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); in gfx_v9_0_write_data_to_reg()
1177 amdgpu_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5)); in gfx_v9_0_wait_reg_mem()
1207 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_UCONFIG_REG, 1)); in gfx_v9_0_ring_test_ring()
1247 ib.ptr[0] = PACKET3(PACKET3_WRITE_DATA, 3); in gfx_v9_0_ring_test_ib()
3349 amdgpu_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0)); in gfx_v9_0_cp_gfx_start()
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H A Dgfx_v11_0.c364 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_SET_RESOURCES, 6)); in gfx11_kiq_set_resources()
400 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_MAP_QUEUES, 5)); in gfx11_kiq_map_queues()
433 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_UNMAP_QUEUES, 4)); in gfx11_kiq_unmap_queues()
460 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_QUERY_STATUS, 5)); in gfx11_kiq_query_status()
523 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); in gfx_v11_0_write_data_to_reg()
536 amdgpu_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5)); in gfx_v11_0_wait_reg_mem()
562 amdgpu_ring_write(ring, PACKET3(PACKET3_NOP, min(num_nop - 2, 0x3ffe))); in gfx_v11_ring_insert_nop()
587 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_UCONFIG_REG, 1)); in gfx_v11_0_ring_test_ring()
640 ib.ptr[0] = PACKET3(PACKET3_WRITE_DATA, 3); in gfx_v11_0_ring_test_ib()
877 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_SET_CONTEXT_REG, 1)); in gfx_v11_0_get_csb_buffer()
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H A Dvid.h105 #define PACKET3(op, n) ((PACKET_TYPE3 << 30) | \ macro
109 #define PACKET3_COMPUTE(op, n) (PACKET3(op, n) | 1 << 1)
H A Dgfx_v12_1.c100 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_SET_RESOURCES, 6)); in gfx_v12_1_kiq_set_resources()
131 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_MAP_QUEUES, 5)); in gfx_v12_1_kiq_map_queues()
163 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_UNMAP_QUEUES, 4)); in gfx_v12_1_kiq_unmap_queues()
189 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_QUERY_STATUS, 5)); in gfx_v12_1_kiq_query_status()
243 amdgpu_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5)); in gfx_v12_1_wait_reg_mem()
284 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_UCONFIG_REG, 1)); in gfx_v12_1_ring_test_ring()
337 ib.ptr[0] = PACKET3(PACKET3_WRITE_DATA, 3); in gfx_v12_1_ring_test_ib()
3371 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1)); in gfx_v12_1_ring_emit_ib_compute()
3375 amdgpu_ring_write(ring, PACKET3(PACKET3_INDIRECT_BUFFER, 2)); in gfx_v12_1_ring_emit_ib_compute()
3393 amdgpu_ring_write(ring, PACKET3(PACKET3_RELEASE_MEM, 6)); in gfx_v12_1_ring_emit_fence()
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H A Dgfx_v12_0.c295 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_SET_RESOURCES, 6)); in gfx_v12_0_kiq_set_resources()
330 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_MAP_QUEUES, 5)); in gfx_v12_0_kiq_map_queues()
363 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_UNMAP_QUEUES, 4)); in gfx_v12_0_kiq_unmap_queues()
389 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_QUERY_STATUS, 5)); in gfx_v12_0_kiq_query_status()
434 amdgpu_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5)); in gfx_v12_0_wait_reg_mem()
471 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_UCONFIG_REG, 1)); in gfx_v12_0_ring_test_ring()
524 ib.ptr[0] = PACKET3(PACKET3_WRITE_DATA, 3); in gfx_v12_0_ring_test_ib()
4450 header = PACKET3(PACKET3_INDIRECT_BUFFER, 2); in gfx_v12_0_ring_emit_ib_gfx()
4473 amdgpu_ring_write(ring, PACKET3(PACKET3_INDIRECT_BUFFER, 2)); in gfx_v12_0_ring_emit_ib_compute()
4491 amdgpu_ring_write(ring, PACKET3(PACKET3_RELEASE_MEM, 6)); in gfx_v12_0_ring_emit_fence()
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H A Damdgpu_gfx.c2492 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_PREAMBLE_CNTL, 0)); in amdgpu_gfx_csb_preamble_start()
2495 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_CONTEXT_CONTROL, 1)); in amdgpu_gfx_csb_preamble_start()
2521 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_SET_CONTEXT_REG, ext->reg_count)); in amdgpu_gfx_csb_data_parser()
2541 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_PREAMBLE_CNTL, 0)); in amdgpu_gfx_csb_preamble_end()
2544 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_CLEAR_STATE, 0)); in amdgpu_gfx_csb_preamble_end()
H A Damdgpu_amdkfd_gfx_v10_3.c302 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_MAP_QUEUES, 5)); in hiq_mqd_load_v10_3()
H A Damdgpu_amdkfd_gfx_v11.c287 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_MAP_QUEUES, 5)); in hiq_mqd_load_v11()
H A Damdgpu_amdkfd_gfx_v10.c316 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_MAP_QUEUES, 5)); in kgd_hiq_mqd_load()
H A Dmes_v12_1.c2046 queue_ptr[wptr++] = PACKET3(PACKET3_SET_UCONFIG_REG, 1); in mes_v12_1_test_ring()
2051 queue_ptr[wptr++] = PACKET3(PACKET3_NOP, 0x3FFF); in mes_v12_1_test_ring()
H A Damdgpu_amdkfd_gfx_v9.c327 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_MAP_QUEUES, 5)); in kgd_gfx_v9_hiq_mqd_load()
/linux/drivers/gpu/drm/radeon/
H A Dni.c1385 radeon_ring_write(ring, PACKET3(PACKET3_SURFACE_SYNC, 3)); in cayman_fence_ring_emit()
1391 radeon_ring_write(ring, PACKET3(PACKET3_EVENT_WRITE_EOP, 4)); in cayman_fence_ring_emit()
1407 radeon_ring_write(ring, PACKET3(PACKET3_MODE_CONTROL, 0)); in cayman_ring_ib_execute()
1412 radeon_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1)); in cayman_ring_ib_execute()
1418 radeon_ring_write(ring, PACKET3(PACKET3_INDIRECT_BUFFER, 2)); in cayman_ring_ib_execute()
1428 radeon_ring_write(ring, PACKET3(PACKET3_SURFACE_SYNC, 3)); in cayman_ring_ib_execute()
1534 radeon_ring_write(ring, PACKET3(PACKET3_ME_INITIALIZE, 5)); in cayman_cp_start()
1552 radeon_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0)); in cayman_cp_start()
1558 radeon_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0)); in cayman_cp_start()
1562 radeon_ring_write(ring, PACKET3(PACKET3_CLEAR_STATE, 0)); in cayman_cp_start()
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H A Dr600.c2697 radeon_ring_write(ring, PACKET3(PACKET3_ME_INITIALIZE, 5)); in r600_cp_start()
2842 radeon_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1)); in r600_ring_test()
2880 radeon_ring_write(ring, PACKET3(PACKET3_SURFACE_SYNC, 3)); in r600_fence_ring_emit()
2886 radeon_ring_write(ring, PACKET3(PACKET3_EVENT_WRITE_EOP, 4)); in r600_fence_ring_emit()
2894 radeon_ring_write(ring, PACKET3(PACKET3_SURFACE_SYNC, 3)); in r600_fence_ring_emit()
2899 radeon_ring_write(ring, PACKET3(PACKET3_EVENT_WRITE, 0)); in r600_fence_ring_emit()
2902 radeon_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1)); in r600_fence_ring_emit()
2906 radeon_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1)); in r600_fence_ring_emit()
2937 radeon_ring_write(ring, PACKET3(PACKET3_MEM_SEMAPHORE, 1)); in r600_semaphore_ring_emit()
2944 radeon_ring_write(ring, PACKET3(PACKET3_PFP_SYNC_ME, 0)); in r600_semaphore_ring_emit()
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H A Dr300d.h64 #define PACKET3(op, n) (CP_PACKET3 | \ macro
H A Dcikd.h1691 #define PACKET3(op, n) ((PACKET_TYPE3 << 30) | \ macro
1695 #define PACKET3_COMPUTE(op, n) (PACKET3(op, n) | 1 << 1)
H A Drv515d.h204 #define PACKET3(op, n) (CP_PACKET3 | \ macro
H A Drv770d.h988 #define PACKET3(op, n) ((RADEON_PACKET_TYPE3 << 30) | \ macro
H A Dnid.h1157 #define PACKET3(op, n) ((RADEON_PACKET_TYPE3 << 30) | \ macro
H A Dr100d.h63 #define PACKET3(op, n) (CP_PACKET3 | \ macro
H A Devergreend.h1543 #define PACKET3(op, n) ((RADEON_PACKET_TYPE3 << 30) | \ macro
H A Dr600d.h1587 #define PACKET3(op, n) ((RADEON_PACKET_TYPE3 << 30) | \ macro
H A Dr100.c940 radeon_ring_write(ring, PACKET3(PACKET3_BITBLT_MULTI, 8)); in r100_copy_blit()