| /linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/ |
| H A D | dcn35_smu.h | 83 #define NUM_FCLK_DPM_LEVELS 8 macro
111 uint32_t FclkClocks_Freq[NUM_FCLK_DPM_LEVELS];
112 uint32_t FclkClocks_Voltage[NUM_FCLK_DPM_LEVELS];
139 uint32_t FclkClocks_Freq[NUM_FCLK_DPM_LEVELS];
140 uint32_t FclkClocks_Voltage[NUM_FCLK_DPM_LEVELS];
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| H A D | dcn35_clk_mgr.c | 938 num_fclk = (clock_table->NumFclkLevelsEnabled > NUM_FCLK_DPM_LEVELS) ? NUM_FCLK_DPM_LEVELS : in dcn35_clk_mgr_helper_populate_bw_params()
998 find_max_clk_value(clock_table->FclkClocks_Freq, NUM_FCLK_DPM_LEVELS); in dcn35_clk_mgr_helper_populate_bw_params()
1200 for (i = 0; i < NUM_FCLK_DPM_LEVELS; i++) { in translate_to_DpmClocks_t_dcn35()
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| /linux/drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/ |
| H A D | smu14_driver_if_v14_0_0.h | 106 #define NUM_FCLK_DPM_LEVELS 8 macro
128 uint32_t FclkClocks_Freq[NUM_FCLK_DPM_LEVELS];
129 uint32_t FclkClocks_Voltage[NUM_FCLK_DPM_LEVELS];
159 uint32_t FclkClocks_Freq[NUM_FCLK_DPM_LEVELS];
160 uint32_t FclkClocks_Voltage[NUM_FCLK_DPM_LEVELS];
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| H A D | smu12_driver_if.h | 107 #define NUM_FCLK_DPM_LEVELS 4 macro
119 DpmClock_t FClocks[NUM_FCLK_DPM_LEVELS];
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| H A D | smu11_driver_if_vangogh.h | 110 #define NUM_FCLK_DPM_LEVELS 4 macro
138 df_pstate_t DfPstateTable[NUM_FCLK_DPM_LEVELS];
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| H A D | smu13_driver_if_aldebaran.h | 34 #define NUM_FCLK_DPM_LEVELS 8 macro
302 uint32_t FidTableFclk[NUM_FCLK_DPM_LEVELS]; //PPCLK_FCLK
303 uint8_t DidTableFclk[NUM_FCLK_DPM_LEVELS]; //PPCLK_FCLK
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| H A D | smu13_driver_if_v13_0_0.h | 44 #define NUM_FCLK_DPM_LEVELS 8 macro
1051 uint16_t FreqTableFclk [NUM_FCLK_DPM_LEVELS ]; // In MHz
1129 …uint8_t FclkDpmUPstates[NUM_FCLK_DPM_LEVELS]; // U P-state ID associated with each FCLK DPM s…
1130 …uint16_t FclkDpmVddU[NUM_FCLK_DPM_LEVELS]; // mV(Q2) Vset U voltage associated with each FCLK …
1131 uint16_t FclkDpmUSpeed[NUM_FCLK_DPM_LEVELS]; //U speed associated with each FCLK DPM state
1411 uint16_t FreqTableFclk [NUM_FCLK_DPM_LEVELS ]; // In MHz
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| H A D | smu13_driver_if_v13_0_7.h | 45 #define NUM_FCLK_DPM_LEVELS 8 macro
1060 uint16_t FreqTableFclk [NUM_FCLK_DPM_LEVELS ]; // In MHz
1131 …uint8_t FclkDpmUPstates[NUM_FCLK_DPM_LEVELS]; // U P-state ID associated with each FCLK DPM s…
1132 …uint16_t FclkDpmVddU[NUM_FCLK_DPM_LEVELS]; // mV(Q2) Vset U voltage associated with each FCLK …
1133 uint16_t FclkDpmUSpeed[NUM_FCLK_DPM_LEVELS]; //U speed associated with each FCLK DPM state
1404 uint16_t FreqTableFclk [NUM_FCLK_DPM_LEVELS ]; // In MHz
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| H A D | smu11_driver_if_arcturus.h | 40 #define NUM_FCLK_DPM_LEVELS 8 macro
50 #define MAX_FCLK_DPM_LEVEL (NUM_FCLK_DPM_LEVELS - 1)
520 uint16_t FreqTableFclk [NUM_FCLK_DPM_LEVELS ]; // In MHz
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| H A D | smu11_driver_if_sienna_cichlid.h | 48 #define NUM_FCLK_DPM_LEVELS 8 macro
67 #define MAX_FCLK_DPM_LEVEL (NUM_FCLK_DPM_LEVELS - 1)
691 uint16_t FreqTableFclk [NUM_FCLK_DPM_LEVELS ]; // In MHz
1051 uint16_t FreqTableFclk [NUM_FCLK_DPM_LEVELS ]; // In MHz
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| H A D | smu_v13_0_6_pmfw.h | 31 #define NUM_FCLK_DPM_LEVELS 4 macro
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| H A D | smu14_driver_if_v14_0.h | 42 #define NUM_FCLK_DPM_LEVELS 8 macro
1151 uint16_t FreqTableFclk [NUM_FCLK_DPM_LEVELS ]; // In MHz
1636 uint16_t FreqTableFclk [NUM_FCLK_DPM_LEVELS ]; // In MHz
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| /linux/drivers/gpu/drm/amd/pm/powerplay/inc/ |
| H A D | smu10_driver_if.h | 102 #define NUM_FCLK_DPM_LEVELS 4 macro
113 DpmClock_t FClocks[NUM_FCLK_DPM_LEVELS];
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| H A D | smu11_driver_if.h | 43 #define NUM_FCLK_DPM_LEVELS 8 macro
58 #define MAX_FCLK_DPM_LEVEL (NUM_FCLK_DPM_LEVELS - 1)
426 uint16_t FreqTableFclk [NUM_FCLK_DPM_LEVELS ];
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| /linux/drivers/gpu/drm/amd/pm/swsmu/smu12/ |
| H A D | renoir_ppt.c | 218 if (dpm_level >= NUM_FCLK_DPM_LEVELS) in renoir_get_dpm_clk_limited()
228 if (dpm_level >= NUM_FCLK_DPM_LEVELS) in renoir_get_dpm_clk_limited()
572 count = NUM_FCLK_DPM_LEVELS; in renoir_print_clk_levels()
774 for (i = 0; i < NUM_FCLK_DPM_LEVELS; i++) { in renoir_get_dpm_clock_table()
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| /linux/drivers/gpu/drm/amd/pm/swsmu/smu11/ |
| H A D | vangogh_ppt.c | 2191 for (i = 0; i < NUM_FCLK_DPM_LEVELS; i++) { in vangogh_get_dpm_clock_table()
2196 for (i = 0; i < NUM_FCLK_DPM_LEVELS; i++) { in vangogh_get_dpm_clock_table()
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| /linux/drivers/gpu/drm/amd/pm/powerplay/hwmgr/ |
| H A D | smu10_hwmgr.c | 516 NUM_FCLK_DPM_LEVELS, in smu10_populate_clock_table()
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| H A D | vega20_hwmgr.c | 3620 PP_ASSERT_WITH_CODE(dpm_table->count <= NUM_FCLK_DPM_LEVELS, in vega20_set_fclk_to_highest_dpm_level()
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