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Searched refs:MC_VM_MX_L1_TLB_CNTL (Results 1 – 4 of 4) sorted by relevance

/linux/drivers/gpu/drm/amd/amdgpu/
H A Dmmhub_v1_0.c144 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 1); in mmhub_v1_0_init_tlb_regs()
145 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, SYSTEM_ACCESS_MODE, 3); in mmhub_v1_0_init_tlb_regs()
146 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, in mmhub_v1_0_init_tlb_regs()
148 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, in mmhub_v1_0_init_tlb_regs()
150 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, in mmhub_v1_0_init_tlb_regs()
152 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ATC_EN, 1); in mmhub_v1_0_init_tlb_regs()
403 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 0); in mmhub_v1_0_gart_disable()
405 MC_VM_MX_L1_TLB_CNTL, in mmhub_v1_0_gart_disable()
/linux/drivers/gpu/drm/radeon/
H A Dni.c1260 WREG32(MC_VM_MX_L1_TLB_CNTL, in cayman_pcie_gart_enable()
1345 WREG32(MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_FRAGMENT_PROCESSING | in cayman_pcie_gart_disable()
H A Dnid.h178 #define MC_VM_MX_L1_TLB_CNTL 0x2064 macro
H A Dcikd.h599 #define MC_VM_MX_L1_TLB_CNTL 0x2064 macro