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Searched refs:MC_SEQ_RAS_TIMING_LP (Results 1 – 11 of 11) sorted by relevance

/linux/drivers/gpu/drm/radeon/
H A Dbtcd.h147 #define MC_SEQ_RAS_TIMING_LP 0x2a6c macro
H A Dbtc_dpm.c1831 *out_reg = MC_SEQ_RAS_TIMING_LP >> 2; in btc_check_s0_mc_reg_index()
2000 WREG32(MC_SEQ_RAS_TIMING_LP, RREG32(MC_SEQ_RAS_TIMING)); in btc_initialize_mc_reg_table()
H A Dnid.h805 #define MC_SEQ_RAS_TIMING_LP 0x2a6c macro
H A Dsid.h573 #define MC_SEQ_RAS_TIMING_LP 0x2a6c macro
H A Dcikd.h698 #define MC_SEQ_RAS_TIMING_LP 0x2a6c macro
H A Devergreend.h323 #define MC_SEQ_RAS_TIMING_LP 0x2a6c macro
H A Dni_dpm.c2777 *out_reg = MC_SEQ_RAS_TIMING_LP >> 2; in ni_check_s0_mc_reg_index()
2886 WREG32(MC_SEQ_RAS_TIMING_LP, RREG32(MC_SEQ_RAS_TIMING)); in ni_initialize_mc_reg_table()
H A Dcypress_dpm.c974 eg_pi->mc_reg_table.mc_reg_address[i].s0 = MC_SEQ_RAS_TIMING_LP >> 2; in cypress_set_mc_reg_address_table()
H A Dci_dpm.c4369 *out_reg = MC_SEQ_RAS_TIMING_LP >> 2; in ci_check_s0_mc_reg_index()
4592 WREG32(MC_SEQ_RAS_TIMING_LP, RREG32(MC_SEQ_RAS_TIMING)); in ci_initialize_mc_reg_table()
H A Dsi_dpm.c5368 *out_reg = MC_SEQ_RAS_TIMING_LP >> 2; in si_check_s0_mc_reg_index()
5481 WREG32(MC_SEQ_RAS_TIMING_LP, RREG32(MC_SEQ_RAS_TIMING)); in si_initialize_mc_reg_table()
/linux/drivers/gpu/drm/amd/amdgpu/
H A Dsid.h574 #define MC_SEQ_RAS_TIMING_LP 0xA9B macro