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Searched refs:MC_SEQ_RAS_TIMING (Results 1 – 11 of 11) sorted by relevance

/linux/drivers/gpu/drm/radeon/
H A Dbtcd.h104 #define MC_SEQ_RAS_TIMING 0x28a0 macro
H A Dbtc_dpm.c1830 case MC_SEQ_RAS_TIMING >> 2: in btc_check_s0_mc_reg_index()
2000 WREG32(MC_SEQ_RAS_TIMING_LP, RREG32(MC_SEQ_RAS_TIMING)); in btc_initialize_mc_reg_table()
H A Dnid.h780 #define MC_SEQ_RAS_TIMING 0x28a0 macro
H A Dsid.h541 #define MC_SEQ_RAS_TIMING 0x28a0 macro
H A Dcikd.h654 #define MC_SEQ_RAS_TIMING 0x28a0 macro
H A Devergreend.h286 #define MC_SEQ_RAS_TIMING 0x28a0 macro
H A Dni_dpm.c2776 case MC_SEQ_RAS_TIMING >> 2: in ni_check_s0_mc_reg_index()
2886 WREG32(MC_SEQ_RAS_TIMING_LP, RREG32(MC_SEQ_RAS_TIMING)); in ni_initialize_mc_reg_table()
H A Dcypress_dpm.c975 eg_pi->mc_reg_table.mc_reg_address[i].s1 = MC_SEQ_RAS_TIMING >> 2; in cypress_set_mc_reg_address_table()
H A Dci_dpm.c4368 case MC_SEQ_RAS_TIMING >> 2: in ci_check_s0_mc_reg_index()
4592 WREG32(MC_SEQ_RAS_TIMING_LP, RREG32(MC_SEQ_RAS_TIMING)); in ci_initialize_mc_reg_table()
H A Dsi_dpm.c5367 case MC_SEQ_RAS_TIMING >> 2: in si_check_s0_mc_reg_index()
5481 WREG32(MC_SEQ_RAS_TIMING_LP, RREG32(MC_SEQ_RAS_TIMING)); in si_initialize_mc_reg_table()
/linux/drivers/gpu/drm/amd/amdgpu/
H A Dsid.h542 #define MC_SEQ_RAS_TIMING 0xA28 macro