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Searched refs:IS_ALDERLAKE_P (Results 1 – 25 of 26) sorted by relevance

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/linux/drivers/gpu/drm/i915/display/
H A Dintel_display_wa.c34 if (IS_ALDERLAKE_P(i915)) in intel_display_wa_apply()
H A Dintel_psr.c1008 if (DISPLAY_VER(display) < 14 && !IS_ALDERLAKE_P(dev_priv)) in hsw_activate_psr2()
1026 if (IS_ALDERLAKE_P(dev_priv) && IS_DISPLAY_STEP(display, STEP_A0, STEP_E0)) { in hsw_activate_psr2()
1093 if (IS_ALDERLAKE_P(dev_priv) || DISPLAY_VER(display) >= 14) in transcoder_has_psr2()
1176 if (IS_ALDERLAKE_P(dev_priv) || DISPLAY_VER(display) >= 14) in dc3co_is_pipe_port_compatible()
1213 if (IS_ALDERLAKE_P(dev_priv) && IS_DISPLAY_STEP(display, STEP_A0, STEP_B0)) in tgl_dc3co_exitline_compute_config()
1276 if (IS_ALDERLAKE_P(dev_priv) || DISPLAY_VER(display) >= 14) in psr2_granularity_check()
1424 if (IS_ALDERLAKE_P(dev_priv) && IS_DISPLAY_STEP(display, STEP_A0, STEP_B0)) { in intel_psr2_config_valid()
1443 (DISPLAY_VER(display) < 14 && !IS_ALDERLAKE_P(dev_priv))) { in intel_psr2_config_valid()
1472 IS_ALDERLAKE_P(dev_priv) && IS_DISPLAY_STEP(display, STEP_A0, STEP_B0)) { in intel_psr2_config_valid()
1907 IS_ALDERLAKE_P(dev_priv))) in intel_psr_enable_source()
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H A Dintel_dmc.c182 } else if (IS_ALDERLAKE_P(i915)) { in dmc_firmware_default()
1001 if (IS_ALDERLAKE_P(i915)) in dmc_fallback_path()
1225 str_yes_no(IS_ALDERLAKE_P(i915) || in intel_dmc_debugfs_status_show()
H A Dintel_display_device.h146 #define HAS_MBUS_JOINING(i915) (IS_ALDERLAKE_P(i915) || DISPLAY_VER(i915) >= 14)
H A Dskl_universal_plane.c529 if (IS_ALDERLAKE_P(i915) && HAS_ASYNC_FLIPS(i915)) in tgl_plane_min_alignment()
2412 if (IS_ALDERLAKE_P(i915) && IS_DISPLAY_STEP(i915, STEP_A0, STEP_B0)) in skl_plane_has_rc_ccs()
2437 if (IS_ALDERLAKE_P(i915) && IS_DISPLAY_STEP(i915, STEP_A0, STEP_B0)) in gen12_plane_has_mc_ccs()
2448 if (DISPLAY_VER(i915) < 13 || IS_ALDERLAKE_P(i915)) in skl_get_plane_caps()
H A Dintel_fb.c1195 return (IS_ALDERLAKE_P(i915) || DISPLAY_VER(i915) >= 14) && in intel_fb_needs_pot_stride_remap()
1335 if ((IS_ALDERLAKE_P(i915) || DISPLAY_VER(i915) >= 14) && in plane_view_scanout_stride()
1543 (IS_ALDERLAKE_P(i915) || DISPLAY_VER(i915) >= 14)) in intel_fb_view_init()
H A Dintel_ddi.c348 if (IS_ALDERLAKE_P(i915) && intel_encoder_is_tc(encoder)) { in intel_ddi_init_dp_buf_reg()
1376 if (IS_ALDERLAKE_P(dev_priv)) { in tgl_dkl_phy_set_signal_levels()
2360 else if (IS_ALDERLAKE_P(i915)) in intel_ddi_splitter_pipe_mask()
3370 } else if (IS_ALDERLAKE_P(dev_priv) && intel_encoder_is_tc(encoder)) { in intel_enable_ddi_hdmi()
3641 if (IS_ALDERLAKE_P(dev_priv) && in intel_ddi_prepare_link_retrain()
4839 return !drm_WARN(&i915->drm, !IS_ALDERLAKE_P(i915) && in assert_has_icl_dsi()
H A Dintel_display_power.c1119 if (IS_ALDERLAKE_P(dev_priv)) in gen12_dbuf_slices_config()
1133 if (IS_ALDERLAKE_P(dev_priv) || DISPLAY_VER(dev_priv) >= 14) in icl_mbus_init()
H A Dicl_dsi.c353 if (IS_ALDERLAKE_S(dev_priv) || IS_ALDERLAKE_P(dev_priv)) { in gen11_dsi_program_esc_clk_div()
374 if (IS_ALDERLAKE_S(dev_priv) || IS_ALDERLAKE_P(dev_priv)) { in gen11_dsi_program_esc_clk_div()
H A Dintel_dpll_mgr.c220 if (IS_ALDERLAKE_P(i915)) in intel_tc_pll_enable_reg()
2603 IS_TIGERLAKE(i915) || IS_ALDERLAKE_S(i915) || IS_ALDERLAKE_P(i915)) && in ehl_combo_pll_div_frac_wa_needed()
3931 if (!(IS_ALDERLAKE_P(i915) && IS_DISPLAY_STEP(i915, STEP_A0, STEP_B0)) || in adlp_cmtg_clock_gating_wa()
4313 else if (IS_ALDERLAKE_P(i915)) in intel_shared_dpll_init()
H A Dintel_ddi_buf_trans.c1712 } else if (IS_ALDERLAKE_P(i915)) { in intel_ddi_buf_trans_init()
H A Dintel_bw.c752 else if (IS_ALDERLAKE_P(dev_priv)) in intel_bw_init_hw()
H A Dintel_cdclk.c3762 } else if (IS_ALDERLAKE_P(dev_priv)) { in intel_init_cdclk_hooks()
3764 if (IS_ALDERLAKE_P(dev_priv) && IS_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0)) { in intel_init_cdclk_hooks()
H A Dintel_display_power_well.c355 if (IS_ALDERLAKE_P(dev_priv) && pg == SKL_PG1) in hsw_power_well_enable()
H A Dintel_dp_mst.c1234 if (!IS_ALDERLAKE_P(i915)) in enable_bs_jitter_was()
H A Dskl_watermark.c3504 else if (IS_ALDERLAKE_P(i915)) in intel_mbus_dbox_update()
3513 } else if (IS_ALDERLAKE_P(i915)) { in intel_mbus_dbox_update()
H A Dintel_bios.c2245 if (INTEL_PCH_TYPE(i915) >= PCH_MTL || IS_ALDERLAKE_P(i915)) { in map_ddc_pin()
H A Dintel_dp.c581 else if (IS_ALDERLAKE_P(dev_priv) || IS_ALDERLAKE_S(dev_priv) || in intel_dp_set_source_rates()
/linux/drivers/gpu/drm/i915/soc/
H A Dintel_pch.c141 !IS_ALDERLAKE_P(dev_priv)); in intel_pch_type()
171 if (IS_ALDERLAKE_S(dev_priv) || IS_ALDERLAKE_P(dev_priv)) in intel_virt_detect_pch()
/linux/drivers/gpu/drm/i915/gt/uc/
H A Dintel_guc_hwconfig.c97 if (IS_ALDERLAKE_P(i915) && !IS_ALDERLAKE_P_N(i915)) in has_table()
/linux/drivers/gpu/drm/i915/gt/
H A Dintel_tlb.c91 IS_ALDERLAKE_P(i915))) in mmio_invalidate_full()
H A Dintel_workarounds.c2245 if (IS_DG2(i915) || IS_ALDERLAKE_P(i915) || IS_ALDERLAKE_S(i915) || in rcs_engine_wa_init()
2258 if (IS_ALDERLAKE_P(i915) || IS_ALDERLAKE_S(i915) || IS_DG1(i915) || in rcs_engine_wa_init()
2278 if (IS_ALDERLAKE_P(i915) || IS_ALDERLAKE_S(i915) || in rcs_engine_wa_init()
2288 if (IS_ROCKETLAKE(i915) || IS_TIGERLAKE(i915) || IS_ALDERLAKE_P(i915)) { in rcs_engine_wa_init()
/linux/drivers/gpu/drm/xe/compat-i915-headers/
H A Di915_drv.h63 #define IS_ALDERLAKE_P(dev_priv) (IS_PLATFORM(dev_priv, XE_ALDERLAKE_P) || \ macro
/linux/drivers/gpu/drm/i915/
H A Dintel_step.c181 } else if (IS_ALDERLAKE_P(i915)) { in intel_step_init()
H A Di915_drv.h530 #define IS_ALDERLAKE_P(i915) IS_PLATFORM(i915, INTEL_ALDERLAKE_P) macro

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