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Searched refs:IP_VER (Results 1 – 25 of 37) sorted by relevance

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/linux/drivers/gpu/drm/i915/gt/
H A Dintel_gt_mcr.c134 } else if (GRAPHICS_VER_FULL(i915) >= IP_VER(12, 70)) { in intel_gt_mcr_init()
136 if (IS_GFX_GT_IP_STEP(gt, IP_VER(12, 70), STEP_A0, STEP_B0) || in intel_gt_mcr_init()
137 IS_GFX_GT_IP_STEP(gt, IP_VER(12, 71), STEP_A0, STEP_B0)) in intel_gt_mcr_init()
164 GRAPHICS_VER_FULL(i915) < IP_VER(12, 55)) { in intel_gt_mcr_init()
216 if (GRAPHICS_VER_FULL(uncore->i915) >= IP_VER(12, 70)) { in rw_with_mcr_steering_fw()
276 if (GRAPHICS_VER_FULL(uncore->i915) >= IP_VER(12, 70) && rw_flag == FW_REG_WRITE) in rw_with_mcr_steering_fw()
278 else if (GRAPHICS_VER_FULL(uncore->i915) < IP_VER(12, 70)) in rw_with_mcr_steering_fw()
340 if (GRAPHICS_VER_FULL(gt->i915) >= IP_VER(12, 70)) { in intel_gt_mcr_lock()
395 if (GRAPHICS_VER_FULL(gt->i915) >= IP_VER(12, 70)) { in intel_gt_mcr_unlock()
420 if (GRAPHICS_VER_FULL(gt->i915) >= IP_VER(12, 70)) in intel_gt_mcr_lock_sanitize()
[all …]
H A Dintel_workarounds.c794 if (!(IS_GFX_GT_IP_STEP(gt, IP_VER(12, 70), STEP_A0, STEP_B0) || in xelpg_ctx_gt_tuning_init()
795 IS_GFX_GT_IP_STEP(gt, IP_VER(12, 71), STEP_A0, STEP_B0))) in xelpg_ctx_gt_tuning_init()
806 if (IS_GFX_GT_IP_STEP(gt, IP_VER(12, 70), STEP_A0, STEP_B0) || in xelpg_ctx_workarounds_init()
807 IS_GFX_GT_IP_STEP(gt, IP_VER(12, 71), STEP_A0, STEP_B0)) { in xelpg_ctx_workarounds_init()
890 if (GRAPHICS_VER_FULL(engine->i915) >= IP_VER(12, 55)) in gen12_ctx_gt_fake_wa_init()
916 if (IS_GFX_GT_IP_RANGE(engine->gt, IP_VER(12, 70), IP_VER(12, 74))) in __intel_engine_init_ctx_wa()
976 if ((IS_GFX_GT_IP_RANGE(rq->engine->gt, IP_VER(12, 70), IP_VER(12, 74)) || in intel_engine_emit_ctx_wa()
1012 if ((IS_GFX_GT_IP_RANGE(rq->engine->gt, IP_VER(12, 70), IP_VER(12, 74)) || in intel_engine_emit_ctx_wa()
1564 if (IS_GFX_GT_IP_STEP(gt, IP_VER(12, 70), STEP_A0, STEP_B0) || in xelpg_gt_workarounds_init()
1565 IS_GFX_GT_IP_STEP(gt, IP_VER(12, 71), STEP_A0, STEP_B0)) { in xelpg_gt_workarounds_init()
[all …]
H A Dgen8_engine_cs.c226 if (IS_GFX_GT_IP_RANGE(rq->engine->gt, IP_VER(12, 70), IP_VER(12, 74)) || in mtl_dummy_pipe_control()
268 if (GRAPHICS_VER_FULL(rq->i915) >= IP_VER(12, 70)) in gen12_emit_flush_rcs()
279 GRAPHICS_VER_FULL(rq->i915) < IP_VER(12, 70)) in gen12_emit_flush_rcs()
824 if (GRAPHICS_VER_FULL(rq->i915) < IP_VER(12, 70)) in gen12_emit_fini_breadcrumb_rcs()
828 if (IS_GFX_GT_IP_RANGE(gt, IP_VER(12, 70), IP_VER(12, 74)) || IS_DG2(i915)) in gen12_emit_fini_breadcrumb_rcs()
833 if (GRAPHICS_VER(i915) == 12 && GRAPHICS_VER_FULL(i915) < IP_VER(12, 55)) in gen12_emit_fini_breadcrumb_rcs()
H A Dintel_gt.h21 BUILD_BUG_ON_ZERO((from) < IP_VER(2, 0)) + \
35 BUILD_BUG_ON_ZERO((from) < IP_VER(13, 0)) + \
H A Dintel_mocs.c461 if (IS_GFX_GT_IP_RANGE(to_gt(i915), IP_VER(12, 70), IP_VER(12, 74))) { in get_mocs_settings()
623 if (GRAPHICS_VER_FULL(gt->i915) >= IP_VER(12, 55)) in init_l3cc_table()
H A Dintel_engine_cs.c769 if (MEDIA_VER_FULL(i915) < IP_VER(12, 55)) in engine_mask_apply_media_fuses()
776 if (MEDIA_VER_FULL(i915) >= IP_VER(12, 55)) { in engine_mask_apply_media_fuses()
1179 if (MEDIA_VER_FULL(i915) == IP_VER(13, 0)) { in intel_engine_init_tlb_invalidation()
1184 if (GRAPHICS_VER_FULL(i915) == IP_VER(12, 74) || in intel_engine_init_tlb_invalidation()
1185 GRAPHICS_VER_FULL(i915) == IP_VER(12, 71) || in intel_engine_init_tlb_invalidation()
1186 GRAPHICS_VER_FULL(i915) == IP_VER(12, 70) || in intel_engine_init_tlb_invalidation()
1187 GRAPHICS_VER_FULL(i915) == IP_VER(12, 55)) { in intel_engine_init_tlb_invalidation()
1190 } else if (GRAPHICS_VER_FULL(i915) == IP_VER(12, 0) || in intel_engine_init_tlb_invalidation()
1191 GRAPHICS_VER_FULL(i915) == IP_VER(12, 10)) { in intel_engine_init_tlb_invalidation()
1810 if (GRAPHICS_VER_FULL(i915) >= IP_VER(12, 55)) { in intel_engine_get_instdone()
H A Dintel_gtt.c28 MEDIA_VER_FULL(i915) == IP_VER(13, 0); in i915_ggtt_require_binder()
681 if (GRAPHICS_VER_FULL(i915) >= IP_VER(12, 70)) in setup_private_pat()
683 else if (GRAPHICS_VER_FULL(i915) >= IP_VER(12, 55)) in setup_private_pat()
H A Dintel_gt_mcr.h57 GRAPHICS_VER_FULL(gt_->i915) >= IP_VER(12, 55) ? \
H A Dintel_rc6.c126 if (IS_GFX_GT_IP_RANGE(gt, IP_VER(12, 70), IP_VER(12, 74))) in gen11_rc6_enable()
527 if (IS_MEDIA_GT_IP_STEP(gt, IP_VER(13, 0), STEP_A0, STEP_B0)) { in rc6_supported()
H A Dintel_reset.c291 loops = GRAPHICS_VER_FULL(gt->i915) < IP_VER(12, 70) ? 2 : 1; in gen6_hw_domain_reset()
709 if (MEDIA_VER_FULL(gt->i915) != IP_VER(13, 0) || !HAS_ENGINE(gt, GSC0)) in needs_wa_14015076503()
1689 if (IS_GFX_GT_IP_STEP(gt, IP_VER(12, 70), STEP_A0, STEP_B0)) in intel_engine_reset_needs_wa_22011802037()
1692 if (GRAPHICS_VER_FULL(gt->i915) >= IP_VER(12, 70)) in intel_engine_reset_needs_wa_22011802037()
H A Dintel_sseu.c640 if (GRAPHICS_VER_FULL(i915) >= IP_VER(12, 55)) in intel_sseu_info_init()
849 else if (GRAPHICS_VER_FULL(i915) >= IP_VER(12, 55)) in intel_sseu_print_topology()
H A Dintel_migrate.c928 if (GRAPHICS_VER_FULL(i915) >= IP_VER(12, 55)) in emit_clear()
939 if (GRAPHICS_VER_FULL(i915) >= IP_VER(12, 55)) { in emit_clear()
/linux/drivers/gpu/drm/i915/gt/uc/
H A Dintel_guc_ads.c415 if (GRAPHICS_VER_FULL(engine->i915) >= IP_VER(12, 55)) in guc_mmio_regset_init()
525 #define LR_HW_CONTEXT_SZ(i915) (GRAPHICS_VER_FULL(i915) >= IP_VER(12, 55) ? \
852 if (IS_GFX_GT_IP_RANGE(gt, IP_VER(12, 70), IP_VER(12, 74))) { in guc_waklv_init()
861 (IS_GFX_GT_IP_RANGE(gt, IP_VER(12, 70), IP_VER(12, 74)) || in guc_waklv_init()
862 IS_MEDIA_GT_IP_RANGE(gt, IP_VER(13, 0), IP_VER(13, 0)) || in guc_waklv_init()
H A Dintel_guc.c297 GRAPHICS_VER_FULL(gt->i915) < IP_VER(12, 55)) in guc_ctl_wa_flags()
301 if (IS_GFX_GT_IP_STEP(gt, IP_VER(12, 70), STEP_A0, STEP_B0) || in guc_ctl_wa_flags()
307 if (IS_GFX_GT_IP_RANGE(gt, IP_VER(12, 70), IP_VER(12, 74))) in guc_ctl_wa_flags()
H A Dintel_guc_hwconfig.c99 if (GRAPHICS_VER_FULL(i915) >= IP_VER(12, 55)) in has_table()
/linux/drivers/gpu/drm/i915/
H A Di915_getparam.c170 if (GRAPHICS_VER_FULL(i915) >= IP_VER(12, 55)) in i915_getparam_ioctl()
179 if (GRAPHICS_VER_FULL(i915) >= IP_VER(12, 55)) in i915_getparam_ioctl()
H A Di915_drv.h397 #define IP_VER(ver, rel) ((ver) << 8 | (rel)) macro
400 #define GRAPHICS_VER_FULL(i915) IP_VER(RUNTIME_INFO(i915)->graphics.ip.ver, \
406 #define MEDIA_VER_FULL(i915) IP_VER(RUNTIME_INFO(i915)->media.ip.ver, \
738 GRAPHICS_VER_FULL(i915) >= IP_VER(12, 70))
H A Dintel_device_info.c317 if (IP_VER(ip->ver, ip->rel) < IP_VER(expected_ver, expected_rel)) in ip_ver_read()
H A Di915_perf.c295 #define HAS_MI_SET_PREDICATE(i915) (GRAPHICS_VER_FULL(i915) >= IP_VER(12, 55))
820 GRAPHICS_VER_FULL(stream->engine->i915) < IP_VER(12, 55)) { in gen8_append_oa_reports()
1422 } else if (GRAPHICS_VER_FULL(stream->engine->i915) >= IP_VER(12, 55)) { in gen12_get_render_context_id()
3194 if (IS_DG2(i915) || IS_GFX_GT_IP_RANGE(gt, IP_VER(12, 70), IP_VER(12, 74))) { in i915_perf_oa_timestamp_frequency()
4091 if (GRAPHICS_VER_FULL(perf->i915) >= IP_VER(12, 55)) { in read_properties_unlocked()
4160 if (IS_MEDIA_GT_IP_STEP(props->engine->gt, IP_VER(13, 0), STEP_A0, STEP_C0) && in read_properties_unlocked()
4458 GRAPHICS_VER_FULL(perf->i915) >= IP_VER(12, 70)) in mtl_is_valid_oam_b_counter_addr()
4473 if (GRAPHICS_VER_FULL(perf->i915) >= IP_VER(12, 70)) in gen12_is_valid_mux_addr()
4833 if (GRAPHICS_VER_FULL(engine->i915) >= IP_VER(1 in __oam_engine_group()
[all...]
H A Di915_irq.c1139 if (GRAPHICS_VER_FULL(dev_priv) >= IP_VER(12, 10)) in intel_irq_handler()
1162 if (GRAPHICS_VER_FULL(dev_priv) >= IP_VER(12, 10)) in intel_irq_reset()
1185 if (GRAPHICS_VER_FULL(dev_priv) >= IP_VER(12, 10)) in intel_irq_postinstall()
H A Di915_debugfs.c146 if (IS_GFX_GT_IP_RANGE(to_gt(i915), IP_VER(12, 70), IP_VER(12, 74))) { in i915_cache_level_str()
H A Dintel_uncore.c2174 if (GRAPHICS_VER_FULL(i915) >= IP_VER(12, 70)) in intel_uncore_fw_domains_init()
2354 if (IS_DGFX(i915) || GRAPHICS_VER_FULL(i915) >= IP_VER(12, 70)) in intel_uncore_setup_mmio()
2429 if (GRAPHICS_VER_FULL(i915) >= IP_VER(12, 70)) { in uncore_forcewake_init()
2433 } else if (GRAPHICS_VER_FULL(i915) >= IP_VER(12, 55)) { in uncore_forcewake_init()
2583 if (GRAPHICS_VER_FULL(uncore->i915) >= IP_VER(12, 55) && i % 2 == 0) { in intel_uncore_prune_engine_fw_domains()
/linux/drivers/gpu/drm/i915/gem/selftests/
H A Di915_gem_client_blt.c120 if (GRAPHICS_VER_FULL(i915) < IP_VER(12, 55)) in fastblit_supports_x_tiling()
169 if (GRAPHICS_VER_FULL(to_i915(batch->base.dev)) >= IP_VER(12, 55)) in prepare_blit()
180 if (GRAPHICS_VER_FULL(to_i915(batch->base.dev)) >= IP_VER(12, 55)) in prepare_blit()
368 } else if (GRAPHICS_VER_FULL(gt->i915) >= IP_VER(12, 55)) { in tiled_offset()
/linux/drivers/gpu/drm/i915/gem/
H A Di915_gem_domain.c351 if (GRAPHICS_VER_FULL(i915) >= IP_VER(12, 70)) in i915_gem_set_caching_ioctl()
H A Di915_gem_create.c409 if (GRAPHICS_VER_FULL(i915) < IP_VER(12, 70)) in ext_set_pat()

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