| /linux/drivers/gpu/drm/amd/amdgpu/ |
| H A D | gfxhub_v3_0_3.c | 235 tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL2, INVALIDATE_L2_CACHE, 1); in gfxhub_v3_0_3_init_cache_regs()
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| H A D | gfxhub_v2_0.c | 229 tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL2, INVALIDATE_L2_CACHE, 1); in gfxhub_v2_0_init_cache_regs()
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| H A D | gfxhub_v11_5_0.c | 233 tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL2, INVALIDATE_L2_CACHE, 1); in gfxhub_v11_5_0_init_cache_regs()
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| H A D | gfxhub_v3_0.c | 230 tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL2, INVALIDATE_L2_CACHE, 1); in gfxhub_v3_0_init_cache_regs()
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| H A D | gfxhub_v12_0.c | 238 tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL2, INVALIDATE_L2_CACHE, 1); in gfxhub_v12_0_init_cache_regs()
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| H A D | mmhub_v3_0_2.c | 249 tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL2, INVALIDATE_L2_CACHE, 1); in mmhub_v3_0_2_init_cache_regs()
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| H A D | mmhub_v3_0_1.c | 257 tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL2, INVALIDATE_L2_CACHE, 1); in mmhub_v3_0_1_init_cache_regs()
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| H A D | mmhub_v3_0.c | 257 tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL2, INVALIDATE_L2_CACHE, 1); in mmhub_v3_0_init_cache_regs()
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| H A D | mmhub_v4_1_0.c | 250 tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL2, INVALIDATE_L2_CACHE, 1); in mmhub_v4_1_0_init_cache_regs()
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| H A D | mmhub_v2_0.c | 303 tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL2, INVALIDATE_L2_CACHE, 1); in mmhub_v2_0_init_cache_regs()
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| H A D | mmhub_v2_3.c | 225 tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL2, INVALIDATE_L2_CACHE, 1); in mmhub_v2_3_init_cache_regs()
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| H A D | mmhub_v1_0.c | 178 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL2, INVALIDATE_L2_CACHE, 1); in mmhub_v1_0_init_cache_regs()
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| H A D | mmhub_v4_2_0.c | 349 INVALIDATE_L2_CACHE, 1); in mmhub_v4_2_0_mid_init_cache_regs()
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| H A D | gmc_v7_0.c | 644 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL2, INVALIDATE_L2_CACHE, 1); in gmc_v7_0_gart_enable()
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| H A D | gmc_v8_0.c | 862 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL2, INVALIDATE_L2_CACHE, 1); in gmc_v8_0_gart_enable()
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| /linux/drivers/gpu/drm/radeon/ |
| H A D | rv770d.h | 649 #define INVALIDATE_L2_CACHE (1 << 1) macro
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| H A D | nid.h | 119 #define INVALIDATE_L2_CACHE (1 << 1) macro
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| H A D | cikd.h | 498 #define INVALIDATE_L2_CACHE (1 << 1) macro
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| H A D | evergreend.h | 1157 #define INVALIDATE_L2_CACHE (1 << 1) macro
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| H A D | r600d.h | 594 #define INVALIDATE_L2_CACHE (1 << 1) macro
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| H A D | ni.c | 1274 WREG32(VM_L2_CNTL2, INVALIDATE_ALL_L1_TLBS | INVALIDATE_L2_CACHE); in cayman_pcie_gart_enable()
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