Searched refs:INVALIDATE_ALL_L1_TLBS (Results 1 – 19 of 19) sorted by relevance
| /linux/drivers/gpu/drm/amd/amdgpu/ |
| H A D | gfxhub_v3_0_3.c | 234 tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL2, INVALIDATE_ALL_L1_TLBS, 1); in gfxhub_v3_0_3_init_cache_regs()
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| H A D | gfxhub_v2_0.c | 228 tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL2, INVALIDATE_ALL_L1_TLBS, 1); in gfxhub_v2_0_init_cache_regs()
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| H A D | gfxhub_v11_5_0.c | 232 tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL2, INVALIDATE_ALL_L1_TLBS, 1); in gfxhub_v11_5_0_init_cache_regs()
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| H A D | mmhub_v3_0_2.c | 247 tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL2, INVALIDATE_ALL_L1_TLBS, 1); in mmhub_v3_0_2_init_cache_regs()
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| H A D | gfxhub_v3_0.c | 229 tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL2, INVALIDATE_ALL_L1_TLBS, 1); in gfxhub_v3_0_init_cache_regs()
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| H A D | gfxhub_v12_0.c | 237 tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL2, INVALIDATE_ALL_L1_TLBS, 1); in gfxhub_v12_0_init_cache_regs()
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| H A D | mmhub_v3_0_1.c | 255 tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL2, INVALIDATE_ALL_L1_TLBS, 1); in mmhub_v3_0_1_init_cache_regs()
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| H A D | mmhub_v3_0.c | 255 tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL2, INVALIDATE_ALL_L1_TLBS, 1); in mmhub_v3_0_init_cache_regs()
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| H A D | mmhub_v2_3.c | 223 tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL2, INVALIDATE_ALL_L1_TLBS, 1); in mmhub_v2_3_init_cache_regs()
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| H A D | mmhub_v2_0.c | 299 tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL2, INVALIDATE_ALL_L1_TLBS, 1); in mmhub_v2_0_init_cache_regs()
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| H A D | mmhub_v3_3.c | 348 tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL2, INVALIDATE_ALL_L1_TLBS, 1); in mmhub_v3_3_init_cache_regs()
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| H A D | mmhub_v4_1_0.c | 248 tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL2, INVALIDATE_ALL_L1_TLBS, 1); in mmhub_v4_1_0_init_cache_regs()
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| H A D | mmhub_v1_0.c | 177 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL2, INVALIDATE_ALL_L1_TLBS, 1); in mmhub_v1_0_init_cache_regs()
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| /linux/drivers/gpu/drm/radeon/ |
| H A D | rv770d.h | 648 #define INVALIDATE_ALL_L1_TLBS (1 << 0) macro
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| H A D | nid.h | 118 #define INVALIDATE_ALL_L1_TLBS (1 << 0) macro
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| H A D | cikd.h | 497 #define INVALIDATE_ALL_L1_TLBS (1 << 0) macro
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| H A D | evergreend.h | 1156 #define INVALIDATE_ALL_L1_TLBS (1 << 0) macro
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| H A D | r600d.h | 593 #define INVALIDATE_ALL_L1_TLBS (1 << 0) macro
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| H A D | ni.c | 1274 WREG32(VM_L2_CNTL2, INVALIDATE_ALL_L1_TLBS | INVALIDATE_L2_CACHE); in cayman_pcie_gart_enable()
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