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Searched refs:I915_NUM_ENGINES (Results 1 – 18 of 18) sorted by relevance

/linux/drivers/gpu/drm/i915/gvt/
H A Dscheduler.h47 struct intel_vgpu_workload *current_workload[I915_NUM_ENGINES];
52 struct intel_vgpu *engine_owner[I915_NUM_ENGINES];
55 struct task_struct *thread[I915_NUM_ENGINES];
56 wait_queue_head_t waitq[I915_NUM_ENGINES];
H A Dgvt.h151 struct intel_vgpu_execlist execlist[I915_NUM_ENGINES];
152 struct list_head workload_q_head[I915_NUM_ENGINES];
153 struct intel_context *shadow[I915_NUM_ENGINES];
160 DECLARE_BITMAP(shadow_ctx_desc_updated, I915_NUM_ENGINES);
161 DECLARE_BITMAP(tlb_handle_pending, I915_NUM_ENGINES);
162 void *ring_scan_buffer[I915_NUM_ENGINES];
163 int ring_scan_buffer_size[I915_NUM_ENGINES];
171 } last_ctx[I915_NUM_ENGINES];
209 u32 hws_pga[I915_NUM_ENGINES];
340 struct notifier_block shadow_ctx_notifier_block[I915_NUM_ENGINES];
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H A Dmmio_context.c162 u32 control_table[I915_NUM_ENGINES][GEN9_MOCS_SIZE];
H A Dcmd_parser.c597 static const struct decode_info *ring_decode_info[I915_NUM_ENGINES][8] = {
/linux/drivers/gpu/drm/i915/selftests/
H A Digt_live_test.h21 unsigned int reset_engine[I915_MAX_GT][I915_NUM_ENGINES];
/linux/drivers/gpu/drm/i915/gt/
H A Dintel_gt_types.h205 struct intel_engine_cs *engine[I915_NUM_ENGINES];
H A Dintel_gt.h187 (id__) < I915_NUM_ENGINES; \
H A Dselftest_timeline.c284 return i915_prandom_u32_max_state(I915_NUM_ENGINES, rnd); in random_engine()
539 timelines = kvmalloc_array(NUM_TIMELINES * I915_NUM_ENGINES, in live_hwsp_engine()
614 timelines = kvmalloc_array(NUM_TIMELINES * I915_NUM_ENGINES, in live_hwsp_alternate()
H A Dintel_engine_types.h143 I915_NUM_ENGINES enumerator
H A Dmock_engine.c347 GEM_BUG_ON(id >= I915_NUM_ENGINES); in mock_engine()
H A Dintel_engine_cs.c478 BUILD_BUG_ON(BITS_PER_TYPE(engine->mask) < I915_NUM_ENGINES); in intel_engine_setup()
965 GENMASK(BITS_PER_TYPE(mask) - 1, I915_NUM_ENGINES)); in intel_engines_init_mmio()
1703 static const i915_reg_t _reg[I915_NUM_ENGINES] = { in __cs_pending_mi_force_wakes()
H A Dselftest_workarounds.c34 } engine[I915_NUM_ENGINES];
H A Dintel_reset.c1607 BUILD_BUG_ON(I915_RESET_ENGINE + I915_NUM_ENGINES > in intel_gt_set_wedged_on_init()
H A Dintel_execlists_submission.c194 } nodes[I915_NUM_ENGINES];
/linux/drivers/gpu/drm/i915/gt/uc/
H A Dintel_guc.h202 u32 ads_regset_count[I915_NUM_ENGINES];
H A Dintel_guc_submission.c5930 BUILD_BUG_ON(ilog2(VIRTUAL_ENGINES) < I915_NUM_ENGINES); in guc_create_virtual()
/linux/drivers/gpu/drm/i915/
H A Dintel_device_info.c393 BUILD_BUG_ON(BITS_PER_TYPE(intel_engine_mask_t) < I915_NUM_ENGINES); in intel_device_info_runtime_init()
/linux/drivers/gpu/drm/i915/gem/
H A Di915_gem_context.c1119 const unsigned int max = I915_NUM_ENGINES; in default_engines()