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/linux/drivers/zorro/
H A Dzorro.ids16 0a00 [SCSI Host Adapter]
22 1300 Warp Engine [Accelerator, SCSI Host Adapter and RAM Expansion]
28 5400 A4091 [SCSI Host Adapter]
31 0100 A2090/A2090A [SCSI Host Adapter]
32 0200 A590/A2091 [SCSI Host Adapter]
33 0300 A590/A2091 [SCSI Host Adapter]
34 0400 A2090B 2090 Autoboot [SCSI Host Adapter]
42 5400 A4091 [SCSI Host Adapter]
49 0300 A2090/A2090A Combitec/MacroSystem [SCSI Host Adapter]
57 0400 Kronos 2000 [SCSI Host Adapter]
[all …]
/linux/Documentation/i2c/busses/
H A Di2c-sis630.rst25 high_clock = [1|0] Forcibly set Host Master Clock to 56KHz (default,
40 00:00.0 Host bridge: Silicon Integrated Systems [SiS] 630 Host (rev 31)
45 00:00.0 Host bridge: Silicon Integrated Systems [SiS] 730 Host (rev 02)
50 00:00.0 Host bridge: Silicon Integrated Systems [SiS] 760/M760 Host (rev 02)
/linux/Documentation/scsi/
H A DBusLogic.rst34 This driver supports all present BusLogic MultiMaster Host Adapters, and should
36 recently, BusLogic introduced the FlashPoint Host Adapters, which are less
38 Despite not having an onboard CPU, the FlashPoint Host Adapters perform very
43 analogous to the firmware on the MultiMaster Host Adapters. Thanks to their
44 having provided the SCCB Manager, this driver now supports the FlashPoint Host
48 to achieve the full performance that BusLogic SCSI Host Adapters and modern
55 The latest information on Linux support for BusLogic SCSI Host Adapters, as
69 the BT-948 PCI Ultra SCSI Host Adapter, and then again for the BT-958 PCI Wide
70 Ultra SCSI Host Adapter in January 1996. This was mutually beneficial since
146 BusLogic SCSI Host Adapters directly implement SCSI-2 Tagged Queuing, and so
[all …]
/linux/drivers/hid/intel-thc-hid/
H A DKconfig8 tristate "Intel Touch Host Controller"
12 THC (Touch Host Controller) is the name of the IP block in PCH that
22 tristate "Intel QuickSPI driver based on Intel Touch Host Controller"
25 Intel QuickSPI, based on Touch Host Controller (THC), implements
33 tristate "Intel QuickI2C driver based on Intel Touch Host Controller"
36 Intel QuickI2C, uses Touch Host Controller (THC) hardware, implements
/linux/drivers/mmc/host/
H A DKconfig6 comment "MMC/SD/SDIO Host Controller Drivers"
68 tristate "Secure Digital Host Controller Interface support"
71 This selects the generic Secure Digital Host Controller Interface.
118 This selects the PCI Secure Digital Host Controller Interface.
157 Host Controller Interface based platform and OF drivers.
170 This selects the Arasan Secure Digital Host Controller Interface
184 This selects the ASPEED Secure Digital Host Controller Interface.
233 This selects the Secure Digital Host Controller Interface (SDHCI)
260 This selects the Secure Digital Host Controller Interface (SDHCI)
272 This selects the Secure Digital Host Controller Interface (SDHCI)
[all …]
/linux/Documentation/driver-api/cxl/platform/acpi/
H A Dcedt.rst12 The CXL Host Bridge Structure describes CXL host bridges. Other than describing
18 Subtable Type : 00 [CXL Host Bridge Structure]
21 Associated host bridge : 00000007 <- Host bridge _UID
48 First Target : 00000007 <- Host Bridge _UID
49 Next Target : 00000006 <- Host Bridge _UID
H A Ddsdt.rst13 Example Compute Express Link Host Bridge ::
19 Name (_HID, "ACPI0016" /* Compute Express Link Host Bridge */) // _HID: Hardware ID
/linux/Documentation/driver-api/cxl/platform/example-configurations/
H A Dhb-interleave.rst4 Cross-Host-Bridge Interleave
18 Subtable Type : 00 [CXL Host Bridge Structure]
27 Subtable Type : 00 [CXL Host Bridge Structure]
96 Name (_HID, "ACPI0016" /* Compute Express Link Host Bridge */) // _HID: Hardware ID
103 Name (_HID, "ACPI0016" /* Compute Express Link Host Bridge */) // _HID: Hardware ID
H A Dmulti-dev-per-hb.rst4 Multiple Devices per Host Bridge
19 Subtable Type : 00 [CXL Host Bridge Structure]
85 Name (_HID, "ACPI0016" /* Compute Express Link Host Bridge */) // _HID: Hardware ID
/linux/Documentation/driver-api/cxl/linux/example-configurations/
H A Dhb-interleave.rst4 Inter-Host-Bridge Interleave
9 * CXL Root has Four (4) CXL Host Bridges
10 * Two CXL Host Bridges have a single CXL Memory Expander Attached
47 Host Bridges. The `Root` can be considered the singular upstream port attached
79 This chunk shows the available downstream ports associated with the CXL Host
143 Host Bridge :code:`port1` has a single decoder (:code:`decoder1.0`), whose only
146 The following chunk shows a similar configuration for Host Bridge :code:`port3`,
H A Dintra-hb-interleave.rst4 Intra-Host-Bridge Interleave
9 * CXL Root has Four (4) CXL Host Bridges
10 * One (1) CXL Host Bridges has two CXL Memory Expanders Attached
11 * The Host bridge decoder is programmed to interleave across the expanders.
47 Host Bridges. The `Root` can be considered the singular upstream port attached
79 This chunk shows the available downstream ports associated with the CXL Host
177 Host Bridge :code:`port1` has a single decoder (:code:`decoder1.0`) with two
H A Dsingle-device.rst9 * CXL Root has Four (4) CXL Host Bridges
10 * One CXL Host Bridges has a single CXL Memory Expander Attached
47 Host Bridges. The `Root` can be considered the singular upstream port attached
79 This chunk shows the available downstream ports associated with the CXL Host
142 Host Bridge :code:`port1` has a single decoder (:code:`decoder1.0`), whose only
H A Dmulti-interleave.rst9 * CXL Root has Four (4) CXL Host Bridges
10 * Two CXL Host Bridges have a two CXL Memory Expanders Attached each.
48 Host Bridges. The `Root` can be considered the singular upstream port attached
80 This chunk shows the available downstream ports associated with the CXL Host
180 Host Bridge :code:`port1` has a single decoder (:code:`decoder1.0`), whose
184 The following chunk shows a similar configuration for Host Bridge :code:`port3`,
/linux/Documentation/ABI/stable/
H A Dsysfs-class-udc6 Indicates if an OTG A-Host supports HNP at an alternate port.
14 Indicates if an OTG A-Host supports HNP at this port.
22 Indicates if an OTG A-Host enabled HNP support.
38 Indicates that this port is the default Host on an OTG session
64 logical disconnection from the USB Host.
/linux/drivers/eisa/
H A Deisa.ids10 ABP0510 "Advansys ABP-510 ISA SCSI Host Adapter"
11 ABP0540 "Advansys ABP-540/542 ISA SCSI Host Adapter"
12 ABP7401 "AdvanSys ABP-740/742 EISA Single Channel SCSI Host Adapter"
13 ABP7501 "AdvanSys ABP-750/752 EISA Dual Channel SCSI Host Adapter"
54 ADP0100 "Adaptec AHA-1540/1542 ISA SCSI Host Adapter"
56 ADP0200 "Adaptec AHA-1520/1522 ISA SCSI Host Adapter"
93 AMI44C1 "AMI SCSI Host Adapter - Series 44"
94 AMI15C1 "AMI SCSI Host Adapter"
95 AMI15D1 "AMI SCSI Host Adapter - Rev 2"
102 AMI4801 "AMI Series 48 EISA Fast SCSI Host Adapter"
[all …]
/linux/Documentation/mhi/
H A Dmhi.rst4 MHI (Modem Host Interface)
34 MHI BHI registers: BHI (Boot Host Interface) registers are used by the host
103 * Host allocates memory for transfer ring.
104 * Host sets the base pointer, read pointer, and write pointer in corresponding
130 * Host allocates memory for event ring.
131 * Host sets the base pointer, read pointer, and write pointer in corresponding
208 * Host prepares TD with buffer information.
209 * Host increments the WP of the corresponding channel transfer ring.
210 * Host rings the channel DB register.
215 * Host wakes up and checks the event ring for completion event.
[all …]
/linux/Documentation/driver-api/cxl/
H A Dtheory-of-operation.rst12 Address space is handled via HDM (Host Managed Device Memory) decoders
25 multiple Host Bridges and endpoints while another may opt for fault tolerance
30 dictates which endpoints can participate in which Host Bridge decode regimes.
33 given range only decodes to one Host Bridge, but that Host Bridge may in turn
39 module generates an emulated CXL topology of 2 Host Bridges each with 2 Root
254 Host Bridges, a PMEM interleave that targets a single Host Bridge, a Volatile
255 memory interleave that spans 2 Host Bridges, and a Volatile memory interleave
256 that only targets a single Host Bridge.
/linux/drivers/hid/intel-ish-hid/
H A DKconfig20 tristate "Host Firmware Load feature for Intel ISH"
28 The Host Firmware Load feature adds support to load the ISH
31 Say M here if you want to support Host Firmware Loading feature
/linux/Documentation/devicetree/bindings/powerpc/4xx/
H A Dakebono.txt14 1.a) The Secure Digital Host Controller Interface (SDHCI) node
16 Represent the Secure Digital Host Controller Interfaces.
24 1.b) The Advanced Host Controller Interface (AHCI) SATA node
/linux/drivers/usb/cdns3/
H A DKconfig9 It supports: dual-role switch, Host-only, and Peripheral-only.
21 It supports: dual-role switch, Host-only, and Peripheral-only.
47 Host controller is compliant with XHCI so it will use
101 It supports: dual-role switch Host-only, and Peripheral-only.
130 Host controller is compliant with XHCI so it uses
/linux/Documentation/ABI/testing/
H A Dsysfs-bus-papr-pmem53 * "HostLCnt" : Host Load Count
54 * "HostSCnt" : Host Store Count
55 * "HostSDur" : Host Store Duration
56 * "HostLDur" : Host Load Duration
/linux/Documentation/usb/
H A Dohci.rst7 The "ohci-hcd" driver is a USB Host Controller Driver (HCD) that is derived
12 It supports the "Open Host Controller Interface" (OHCI), which standardizes
14 compared to the earlier "Universal Host Controller Interface" (UHCI) from
/linux/drivers/bus/mhi/ep/
H A DKconfig2 tristate "Modem Host Interface (MHI) bus Endpoint implementation"
4 Bus driver for MHI protocol. Modem Host Interface (MHI) is a
/linux/Documentation/driver-api/cxl/linux/
H A Dcxl-driver.rst80 * `Host Bridge Ports` defined by CHBS in the :doc:`CEDT<../platform/acpi/cedt>`
82 * `Downstream Ports` typically connected to `Host Bridge Ports`.
129 CXL `Host Bridges` in the fabric are probed during :code:`cxl_acpi_probe` at
140 A `Host Bridge` is a special type of CXL `switch port`. It is explicitly
141 defined in the ACPI specification via `ACPI0016` ID. `Host Bridge` ports
204 A `Decoder` is short for a CXL Host-Managed Device Memory (HDM) Decoder. It is
206 the endpoint translates a `Host Physical` to `Device Physical` Addressing.
209 engage in translation of `Host Physical Address` to `Device Physical Address`.
215 CXL Host Bridge and Upstream Switch Port Decode Flow
263 of a root decoder are `Host Bridges`, which means interleave done at the root
[all …]
/linux/Documentation/userspace-api/media/v4l/
H A Dpipeline.dot6 …scaler [label="{<scaler_0> 0} | Host\nScaler | {<scaler_1> 1} ", shape=Mrecord, style=filled, fill…
7 …frontend [label="{<frontend_0> 0} | Host\nFrontend | {<frontend_1> 1}", shape=Mrecord, style=fille…

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