| /linux/drivers/gpu/drm/radeon/ |
| H A D | ni.c | 1639 WREG32(GRBM_SOFT_RESET, (SOFT_RESET_CP | in cayman_cp_resume() 1645 RREG32(GRBM_SOFT_RESET); in cayman_cp_resume() 1647 WREG32(GRBM_SOFT_RESET, 0); in cayman_cp_resume() 1648 RREG32(GRBM_SOFT_RESET); in cayman_cp_resume() 1894 tmp = RREG32(GRBM_SOFT_RESET); in cayman_gpu_soft_reset() 1897 WREG32(GRBM_SOFT_RESET, tmp); in cayman_gpu_soft_reset() 1898 tmp = RREG32(GRBM_SOFT_RESET); in cayman_gpu_soft_reset() 1903 WREG32(GRBM_SOFT_RESET, tmp); in cayman_gpu_soft_reset() 1904 tmp = RREG32(GRBM_SOFT_RESET); in cayman_gpu_soft_reset()
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| H A D | rv770.c | 1105 WREG32(GRBM_SOFT_RESET, SOFT_RESET_CP); in rv770_cp_load_microcode() 1106 RREG32(GRBM_SOFT_RESET); in rv770_cp_load_microcode() 1108 WREG32(GRBM_SOFT_RESET, 0); in rv770_cp_load_microcode()
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| H A D | r600.c | 2661 WREG32(GRBM_SOFT_RESET, SOFT_RESET_CP); in r600_cp_load_microcode() 2662 RREG32(GRBM_SOFT_RESET); in r600_cp_load_microcode() 2664 WREG32(GRBM_SOFT_RESET, 0); in r600_cp_load_microcode() 2724 WREG32(GRBM_SOFT_RESET, SOFT_RESET_CP); in r600_cp_resume() 2725 RREG32(GRBM_SOFT_RESET); in r600_cp_resume() 2727 WREG32(GRBM_SOFT_RESET, 0); in r600_cp_resume()
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| H A D | rv770d.h | 401 #define GRBM_SOFT_RESET 0x8020 macro
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| H A D | nid.h | 280 #define GRBM_SOFT_RESET 0x8020 macro
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| H A D | cikd.h | 1075 #define GRBM_SOFT_RESET 0x8020 macro
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| H A D | evergreend.h | 828 #define GRBM_SOFT_RESET 0x8020 macro
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| H A D | r600d.h | 295 #define GRBM_SOFT_RESET 0x8020 macro
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| /linux/drivers/gpu/drm/amd/amdgpu/ |
| H A D | gfx_v11_0.c | 2294 WREG32_FIELD15_PREREG(GC, 0, GRBM_SOFT_RESET, SOFT_RESET_RLC, 1); in gfx_v11_0_rlc_smu_handshake_cntl() 2296 WREG32_FIELD15_PREREG(GC, 0, GRBM_SOFT_RESET, SOFT_RESET_RLC, 0); in gfx_v11_0_rlc_smu_handshake_cntl() 5203 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset, GRBM_SOFT_RESET, in gfx_v11_0_check_soft_reset() 5205 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset, GRBM_SOFT_RESET, in gfx_v11_0_check_soft_reset() 5207 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset, GRBM_SOFT_RESET, in gfx_v11_0_check_soft_reset() 5209 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset, GRBM_SOFT_RESET, in gfx_v11_0_check_soft_reset() 5211 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset, GRBM_SOFT_RESET, in gfx_v11_0_check_soft_reset() 5216 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset, GRBM_SOFT_RESET, in gfx_v11_0_post_soft_reset() 5218 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset, GRBM_SOFT_RESET, in gfx_v11_0_post_soft_reset() 5220 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset, GRBM_SOFT_RESET, in gfx_v11_0_post_soft_reset() [all...] |
| H A D | gfx_v9_0.c | 3132 WREG32_FIELD15(GC, 0, GRBM_SOFT_RESET, SOFT_RESET_RLC, 1); in gfx_v9_0_rlc_reset() 3134 WREG32_FIELD15(GC, 0, GRBM_SOFT_RESET, SOFT_RESET_RLC, 0); in gfx_v9_0_rlc_reset() 4173 GRBM_SOFT_RESET, SOFT_RESET_CP, 1); in gfx_v9_0_soft_reset() 4175 GRBM_SOFT_RESET, SOFT_RESET_GFX, 1); in gfx_v9_0_soft_reset() 4180 GRBM_SOFT_RESET, SOFT_RESET_CP, 1); in gfx_v9_0_soft_reset() 4187 GRBM_SOFT_RESET, SOFT_RESET_RLC, 1); in gfx_v9_0_soft_reset() 4203 dev_info(adev->dev, "GRBM_SOFT_RESET=0x%08X\n", tmp); in gfx_v9_0_kiq_read_clock()
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| H A D | gfx_v6_0.c | 2547 WREG32_FIELD(GRBM_SOFT_RESET, SOFT_RESET_RLC, 1); in gfx_v6_0_rlc_reset() 2549 WREG32_FIELD(GRBM_SOFT_RESET, SOFT_RESET_RLC, 0); in gfx_v6_0_rlc_reset()
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| H A D | gfx_v12_1.c | 1596 GRBM_SOFT_RESET, SOFT_RESET_RLC, 1); in gfx_v12_1_xcc_rlc_start() 1599 GRBM_SOFT_RESET, SOFT_RESET_RLC, 0); in gfx_v12_1_xcc_rlc_start()
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| H A D | gfx_v12_0.c | 1935 WREG32_FIELD15_PREREG(GC, 0, GRBM_SOFT_RESET, SOFT_RESET_RLC, 1); in gfx_v12_0_rlc_reset() 1937 WREG32_FIELD15_PREREG(GC, 0, GRBM_SOFT_RESET, SOFT_RESET_RLC, 0); in gfx_v12_0_rlc_reset()
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