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Searched refs:GENMASK (Results 1 – 25 of 1585) sorted by relevance

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/linux/include/soc/mscc/
H A Docelot_ana.h15 #define ANA_ANAGEFIL_PID_VAL(x) (((x) << 14) & GENMASK(18, 14))
16 #define ANA_ANAGEFIL_PID_VAL_M GENMASK(18, 14)
17 #define ANA_ANAGEFIL_PID_VAL_X(x) (((x) & GENMASK(18, 14)) >> 14)
19 #define ANA_ANAGEFIL_VID_VAL(x) ((x) & GENMASK(12, 0))
20 #define ANA_ANAGEFIL_VID_VAL_M GENMASK(12, 0)
24 #define ANA_STORMLIMIT_CFG_STORM_RATE(x) (((x) << 3) & GENMASK(6, 3))
25 #define ANA_STORMLIMIT_CFG_STORM_RATE_M GENMASK(6, 3)
26 #define ANA_STORMLIMIT_CFG_STORM_RATE_X(x) (((x) & GENMASK(6, 3)) >> 3)
28 #define ANA_STORMLIMIT_CFG_STORM_MODE(x) ((x) & GENMASK(1, 0))
29 #define ANA_STORMLIMIT_CFG_STORM_MODE_M GENMASK(1, 0)
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H A Docelot_hsio.h90 #define HSIO_PLL5G_CFG0_SELBGV820(x) (((x) << 23) & GENMASK(26, 23))
91 #define HSIO_PLL5G_CFG0_SELBGV820_M GENMASK(26, 23)
92 #define HSIO_PLL5G_CFG0_SELBGV820_X(x) (((x) & GENMASK(26, 23)) >> 23)
93 #define HSIO_PLL5G_CFG0_LOOP_BW_RES(x) (((x) << 18) & GENMASK(22, 18))
94 #define HSIO_PLL5G_CFG0_LOOP_BW_RES_M GENMASK(22, 18)
95 #define HSIO_PLL5G_CFG0_LOOP_BW_RES_X(x) (((x) & GENMASK(22, 18)) >> 18)
96 #define HSIO_PLL5G_CFG0_SELCPI(x) (((x) << 16) & GENMASK(17, 16))
97 #define HSIO_PLL5G_CFG0_SELCPI_M GENMASK(17, 16)
98 #define HSIO_PLL5G_CFG0_SELCPI_X(x) (((x) & GENMASK(17, 16)) >> 16)
103 #define HSIO_PLL5G_CFG0_CPU_CLK_DIV(x) (((x) << 6) & GENMASK(11, 6))
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H A Docelot_qsys.h25 #define QSYS_EEE_THRES_EEE_HIGH_BYTES(x) (((x) << 8) & GENMASK(15, 8))
26 #define QSYS_EEE_THRES_EEE_HIGH_BYTES_M GENMASK(15, 8)
27 #define QSYS_EEE_THRES_EEE_HIGH_BYTES_X(x) (((x) & GENMASK(15, 8)) >> 8)
28 #define QSYS_EEE_THRES_EEE_HIGH_FRAMES(x) ((x) & GENMASK(7, 0))
29 #define QSYS_EEE_THRES_EEE_HIGH_FRAMES_M GENMASK(7, 0)
33 #define QSYS_EXT_CPU_CFG_EXT_CPU_PORT(x) (((x) << 8) & GENMASK(12, 8))
34 #define QSYS_EXT_CPU_CFG_EXT_CPU_PORT_M GENMASK(12, 8)
35 #define QSYS_EXT_CPU_CFG_EXT_CPU_PORT_X(x) (((x) & GENMASK(12, 8)) >> 8)
36 #define QSYS_EXT_CPU_CFG_EXT_CPUQ_MSK(x) ((x) & GENMASK(7, 0))
37 #define QSYS_EXT_CPU_CFG_EXT_CPUQ_MSK_M GENMASK(7, 0)
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H A Docelot_sys.h20 #define SYS_FRM_AGING_MAX_AGE(x) ((x) & GENMASK(19, 0))
21 #define SYS_FRM_AGING_MAX_AGE_M GENMASK(19, 0)
23 #define SYS_STAT_CFG_STAT_CLEAR_SHOT(x) (((x) << 10) & GENMASK(16, 10))
24 #define SYS_STAT_CFG_STAT_CLEAR_SHOT_M GENMASK(16, 10)
25 #define SYS_STAT_CFG_STAT_CLEAR_SHOT_X(x) (((x) & GENMASK(16, 10)) >> 10)
26 #define SYS_STAT_CFG_STAT_VIEW(x) ((x) & GENMASK(9, 0))
27 #define SYS_STAT_CFG_STAT_VIEW_M GENMASK(9, 0)
40 #define SYS_TIMESTAMP_OFFSET_ETH_TYPE_CFG(x) (((x) << 6) & GENMASK(21, 6))
41 #define SYS_TIMESTAMP_OFFSET_ETH_TYPE_CFG_M GENMASK(21, 6)
42 #define SYS_TIMESTAMP_OFFSET_ETH_TYPE_CFG_X(x) (((x) & GENMASK(21, 6)) >> 6)
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H A Docelot_dev.h17 #define DEV_CLOCK_CFG_LINK_SPEED(x) ((x) & GENMASK(1, 0))
18 #define DEV_CLOCK_CFG_LINK_SPEED_M GENMASK(1, 0)
27 #define DEV_EEE_CFG_EEE_TIMER_AGE(x) (((x) << 15) & GENMASK(21, 15))
28 #define DEV_EEE_CFG_EEE_TIMER_AGE_M GENMASK(21, 15)
29 #define DEV_EEE_CFG_EEE_TIMER_AGE_X(x) (((x) & GENMASK(21, 15)) >> 15)
30 #define DEV_EEE_CFG_EEE_TIMER_WAKEUP(x) (((x) << 8) & GENMASK(14, 8))
31 #define DEV_EEE_CFG_EEE_TIMER_WAKEUP_M GENMASK(14, 8)
32 #define DEV_EEE_CFG_EEE_TIMER_WAKEUP_X(x) (((x) & GENMASK(14, 8)) >> 8)
33 #define DEV_EEE_CFG_EEE_TIMER_HOLDOFF(x) (((x) << 1) & GENMASK(7, 1))
34 #define DEV_EEE_CFG_EEE_TIMER_HOLDOFF_M GENMASK(7, 1)
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/linux/drivers/ras/amd/atl/
H A Dreg_fields.h37 #define DF2_COH_ST_FABRIC_ID GENMASK(19, 8)
38 #define DF4p5_COH_ST_FABRIC_ID GENMASK(15, 8)
60 #define DF3_COMPONENT_ID_MASK GENMASK(9, 0)
61 #define DF4_COMPONENT_ID_MASK GENMASK(15, 0)
82 #define DF2_DST_FABRIC_ID GENMASK(7, 0)
83 #define DF3_DST_FABRIC_ID GENMASK(9, 0)
84 #define DF3p5_DST_FABRIC_ID GENMASK(11, 0)
85 #define DF4_DST_FABRIC_ID GENMASK(27, 16)
86 #define DF4p5_DST_FABRIC_ID GENMASK(23, 16)
109 #define DF2_DIE_ID_MASK GENMASK(15, 8)
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/linux/drivers/hid/intel-thc-hid/intel-thc/
H A Dintel-thc-hw.h246 #define THC_CFG_DID_VID_VID GENMASK(15, 0)
247 #define THC_CFG_DID_VID_DID GENMASK(31, 16)
264 #define THC_CFG_STS_CMD_DEVT GENMASK(26, 25)
271 #define THC_CFG_CC_RID_RID GENMASK(7, 0)
272 #define THC_CFG_CC_RID_PI GENMASK(15, 8)
273 #define THC_CFG_CC_RID_SCC GENMASK(23, 16)
274 #define THC_CFG_CC_RID_BCC GENMASK(31, 24)
276 #define THC_CFG_BIST_HTYPE_LT_CLS_CLSZ GENMASK(7, 0)
277 #define THC_CFG_BIST_HTYPE_LT_CLS_LT GENMASK(15, 8)
278 #define THC_CFG_BIST_HTYPE_LT_CLS_HTYPE GENMASK(22, 16)
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/linux/drivers/net/ethernet/mediatek/
H A Dmtk_wed_regs.h8 #define MTK_WDMA_DESC_CTRL_LEN1 GENMASK(14, 0)
9 #define MTK_WDMA_DESC_CTRL_LEN1_V2 GENMASK(13, 0)
12 #define MTK_WDMA_DESC_CTRL_LEN0 GENMASK(29, 16)
109 #define MTK_WED_STATUS_TX GENMASK(15, 8)
112 #define MTK_WED_WPDMA_STATUS_TX_DRV GENMASK(15, 8)
115 #define MTK_WED_TX_BM_CTRL_VLD_GRP_NUM GENMASK(6, 0)
116 #define MTK_WED_TX_BM_CTRL_RSV_GRP_NUM GENMASK(22, 16)
123 #define MTK_WED_TX_BM_SW_TAIL_IDX GENMASK(16, 0)
126 #define MTK_WED_TX_BM_TKID_START GENMASK(15, 0)
127 #define MTK_WED_TX_BM_TKID_END GENMASK(31, 16)
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H A Dmtk_ppe_regs.h43 #define MTK_PPE_IP_PROTO_CHK_IPV4 GENMASK(15, 0)
44 #define MTK_PPE_IP_PROTO_CHK_IPV6 GENMASK(31, 16)
47 #define MTK_PPE_TB_CFG_ENTRY_NUM GENMASK(2, 0)
49 #define MTK_PPE_TB_CFG_SEARCH_MISS GENMASK(5, 4)
56 #define MTK_PPE_TB_CFG_KEEPALIVE GENMASK(13, 12)
57 #define MTK_PPE_TB_CFG_HASH_MODE GENMASK(15, 14)
58 #define MTK_PPE_TB_CFG_SCAN_MODE GENMASK(17, 16)
59 #define MTK_PPE_TB_CFG_HASH_DEBUG GENMASK(19, 18)
64 #define MTK_PPE_NTU_KEEPALIVE GENMASK(23, 16)
89 #define MTK_PPE_TB_USED_NUM GENMASK(13, 0)
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/linux/drivers/media/platform/ti/cal/
H A Dcal_regs.h91 #define CAL_HL_REVISION_MINOR_MASK GENMASK(5, 0)
92 #define CAL_HL_REVISION_CUSTOM_MASK GENMASK(7, 6)
93 #define CAL_HL_REVISION_MAJOR_MASK GENMASK(10, 8)
94 #define CAL_HL_REVISION_RTL_MASK GENMASK(15, 11)
95 #define CAL_HL_REVISION_FUNC_MASK GENMASK(27, 16)
96 #define CAL_HL_REVISION_SCHEME_MASK GENMASK(31, 30)
100 #define CAL_HL_HWINFO_WFIFO_MASK GENMASK(3, 0)
101 #define CAL_HL_HWINFO_RFIFO_MASK GENMASK(7, 4)
102 #define CAL_HL_HWINFO_PCTX_MASK GENMASK(12, 8)
103 #define CAL_HL_HWINFO_WCTX_MASK GENMASK(18, 13)
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/linux/drivers/net/can/ctucanfd/
H A Dctucanfd_kregs.h98 #define REG_DEVICE_ID_DEVICE_ID GENMASK(15, 0)
99 #define REG_DEVICE_ID_VER_MINOR GENMASK(23, 16)
100 #define REG_DEVICE_ID_VER_MAJOR GENMASK(31, 24)
115 #define REG_MODE_RTRTH GENMASK(20, 17)
159 #define REG_INT_ENA_SET_INT_ENA_SET GENMASK(11, 0)
162 #define REG_INT_ENA_CLR_INT_ENA_CLR GENMASK(11, 0)
165 #define REG_INT_MASK_SET_INT_MASK_SET GENMASK(11, 0)
168 #define REG_INT_MASK_CLR_INT_MASK_CLR GENMASK(11, 0)
171 #define REG_BTR_PROP GENMASK(6, 0)
172 #define REG_BTR_PH1 GENMASK(12, 7)
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/linux/drivers/gpu/drm/mediatek/
H A Dmtk_dp_reg.h17 #define RG_XTP_GLB_BIAS_INTR_CTRL GENMASK(20, 16)
19 #define RG_CKM_PT0_CKTX_IMPSEL GENMASK(23, 20)
38 #define RG_XTP_LN0_TX_IMPSEL_PMOS GENMASK(15, 12)
39 #define RG_XTP_LN0_TX_IMPSEL_NMOS GENMASK(19, 16)
41 #define RG_XTP_LN1_TX_IMPSEL_PMOS GENMASK(15, 12)
42 #define RG_XTP_LN1_TX_IMPSEL_NMOS GENMASK(19, 16)
44 #define RG_XTP_LN2_TX_IMPSEL_PMOS GENMASK(15, 12)
45 #define RG_XTP_LN2_TX_IMPSEL_NMOS GENMASK(19, 16)
47 #define RG_XTP_LN3_TX_IMPSEL_PMOS GENMASK(15, 12)
48 #define RG_XTP_LN3_TX_IMPSEL_NMOS GENMASK(19, 16)
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/linux/drivers/net/ipa/reg/
H A Dipa_reg-v5.0.c13 [MAX_PIPES] = GENMASK(7, 0),
14 [MAX_CONS_PIPES] = GENMASK(15, 8),
15 [MAX_PROD_PIPES] = GENMASK(23, 16),
16 [PROD_LOWEST] = GENMASK(31, 24),
44 [ATOMIC_FETCHER_ARB_LOCK_DIS] = GENMASK(27, 22),
90 [ROUTE_DEF_PIPE] = GENMASK(7, 0),
91 [ROUTE_FRAG_DEF_PIPE] = GENMASK(15, 8),
92 [ROUTE_DEF_HDR_OFST] = GENMASK(25, 16),
102 [MEM_SIZE] = GENMASK(15, 0),
103 [MEM_BADDR] = GENMASK(31, 16),
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H A Dipa_reg-v5.5.c13 [MAX_PIPES] = GENMASK(7, 0),
14 [MAX_CONS_PIPES] = GENMASK(15, 8),
15 [MAX_PROD_PIPES] = GENMASK(23, 16),
16 [PROD_LOWEST] = GENMASK(31, 24),
43 [ATOMIC_FETCHER_ARB_LOCK_DIS] = GENMASK(27, 22),
89 [ROUTE_DEF_PIPE] = GENMASK(7, 0),
90 [ROUTE_FRAG_DEF_PIPE] = GENMASK(15, 8),
91 [ROUTE_DEF_HDR_OFST] = GENMASK(25, 16),
101 [MEM_SIZE] = GENMASK(15, 0),
102 [MEM_BADDR] = GENMASK(31, 16),
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H A Dipa_reg-v3.1.c48 [ROUTE_DEF_PIPE] = GENMASK(5, 1),
50 [ROUTE_DEF_HDR_OFST] = GENMASK(16, 7),
51 [ROUTE_FRAG_DEF_PIPE] = GENMASK(21, 17),
60 [MEM_SIZE] = GENMASK(15, 0),
61 [MEM_BADDR] = GENMASK(31, 16),
67 [GEN_QMB_0_MAX_WRITES] = GENMASK(3, 0),
68 [GEN_QMB_1_MAX_WRITES] = GENMASK(7, 4),
75 [GEN_QMB_0_MAX_READS] = GENMASK(3, 0),
76 [GEN_QMB_1_MAX_READS] = GENMASK(7, 4),
100 [IPA_BASE_ADDR] = GENMASK(16, 0),
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H A Dipa_reg-v4.5.c30 [ATOMIC_FETCHER_ARB_LOCK_DIS] = GENMASK(20, 17),
76 [ROUTE_DEF_PIPE] = GENMASK(5, 1),
78 [ROUTE_DEF_HDR_OFST] = GENMASK(16, 7),
79 [ROUTE_FRAG_DEF_PIPE] = GENMASK(21, 17),
88 [MEM_SIZE] = GENMASK(15, 0),
89 [MEM_BADDR] = GENMASK(31, 16),
95 [GEN_QMB_0_MAX_WRITES] = GENMASK(3, 0),
96 [GEN_QMB_1_MAX_WRITES] = GENMASK(7, 4),
103 [GEN_QMB_0_MAX_READS] = GENMASK(3, 0),
104 [GEN_QMB_1_MAX_READS] = GENMASK(7, 4),
[all …]
H A Dipa_reg-v4.9.c34 [ATOMIC_FETCHER_ARB_LOCK_DIS] = GENMASK(24, 22),
81 [ROUTE_DEF_PIPE] = GENMASK(5, 1),
83 [ROUTE_DEF_HDR_OFST] = GENMASK(16, 7),
84 [ROUTE_FRAG_DEF_PIPE] = GENMASK(21, 17),
93 [MEM_SIZE] = GENMASK(15, 0),
94 [MEM_BADDR] = GENMASK(31, 16),
100 [GEN_QMB_0_MAX_WRITES] = GENMASK(3, 0),
101 [GEN_QMB_1_MAX_WRITES] = GENMASK(7, 4),
108 [GEN_QMB_0_MAX_READS] = GENMASK(3, 0),
109 [GEN_QMB_1_MAX_READS] = GENMASK(7, 4),
[all …]
H A Dipa_reg-v4.11.c35 [ATOMIC_FETCHER_ARB_LOCK_DIS] = GENMASK(23, 22),
82 [ROUTE_DEF_PIPE] = GENMASK(5, 1),
84 [ROUTE_DEF_HDR_OFST] = GENMASK(16, 7),
85 [ROUTE_FRAG_DEF_PIPE] = GENMASK(21, 17),
94 [MEM_SIZE] = GENMASK(15, 0),
95 [MEM_BADDR] = GENMASK(31, 16),
101 [GEN_QMB_0_MAX_WRITES] = GENMASK(3, 0),
102 [GEN_QMB_1_MAX_WRITES] = GENMASK(7, 4),
109 [GEN_QMB_0_MAX_READS] = GENMASK(3, 0),
110 [GEN_QMB_1_MAX_READS] = GENMASK(7, 4),
[all …]
H A Dipa_reg-v4.7.c30 [ATOMIC_FETCHER_ARB_LOCK_DIS] = GENMASK(20, 17),
76 [ROUTE_DEF_PIPE] = GENMASK(5, 1),
78 [ROUTE_DEF_HDR_OFST] = GENMASK(16, 7),
79 [ROUTE_FRAG_DEF_PIPE] = GENMASK(21, 17),
88 [MEM_SIZE] = GENMASK(15, 0),
89 [MEM_BADDR] = GENMASK(31, 16),
95 [GEN_QMB_0_MAX_WRITES] = GENMASK(3, 0),
96 [GEN_QMB_1_MAX_WRITES] = GENMASK(7, 4),
103 [GEN_QMB_0_MAX_READS] = GENMASK(3, 0),
104 [GEN_QMB_1_MAX_READS] = GENMASK(7, 4),
[all …]
/linux/drivers/mtd/nand/raw/
H A Ddenali.h24 #define LOAD_WAIT_CNT__VALUE GENMASK(15, 0)
27 #define PROGRAM_WAIT_CNT__VALUE GENMASK(15, 0)
30 #define ERASE_WAIT_CNT__VALUE GENMASK(15, 0)
33 #define INT_MON_CYCCNT__VALUE GENMASK(15, 0)
55 #define PREFETCH_MODE__PREFETCH_BURST_LENGTH GENMASK(15, 4)
67 #define TWHR2_AND_WE_2_RE__WE_2_RE GENMASK(5, 0)
68 #define TWHR2_AND_WE_2_RE__TWHR2 GENMASK(13, 8)
72 #define TCWAW_AND_ADDR_2_DATA__ADDR_2_DATA GENMASK(6, 0)
73 #define TCWAW_AND_ADDR_2_DATA__TCWAW GENMASK(13, 8)
76 #define RE_2_WE__VALUE GENMASK(5, 0)
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/linux/drivers/net/wwan/t7xx/
H A Dt7xx_hif_dpmaif_rx.h25 #define NETIF_MASK GENMASK(4, 0)
48 #define PD_PIT_DATA_LEN GENMASK(31, 16)
49 #define PD_PIT_BUFFER_ID GENMASK(15, 3)
54 #define PD_PIT_DLQ_DONE GENMASK(31, 30)
55 #define PD_PIT_ULQ_DONE GENMASK(29, 24)
56 #define PD_PIT_HEADER_OFFSET GENMASK(23, 19)
57 #define PD_PIT_BI_F GENMASK(18, 17)
59 #define PD_PIT_RES GENMASK(15, 11)
60 #define PD_PIT_H_BID GENMASK(10, 8)
61 #define PD_PIT_PIT_SEQ GENMASK(7, 0)
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/linux/drivers/net/wireless/mediatek/mt7601u/
H A Dregs.h22 #define MT_EFUSE_CTRL_AOUT GENMASK(5, 0)
23 #define MT_EFUSE_CTRL_MODE GENMASK(7, 6)
24 #define MT_EFUSE_CTRL_LDO_OFF_TIME GENMASK(13, 8)
25 #define MT_EFUSE_CTRL_LDO_ON_TIME GENMASK(15, 14)
26 #define MT_EFUSE_CTRL_AIN GENMASK(25, 16)
52 #define MT_WLAN_FUN_CTRL_GPIO_IN GENMASK(15, 8) /* MT76x0 */
53 #define MT_WLAN_FUN_CTRL_GPIO_OUT GENMASK(23, 16) /* MT76x0 */
54 #define MT_WLAN_FUN_CTRL_GPIO_OUT_EN GENMASK(31, 24) /* MT76x0 */
63 #define MT_XO_CTRL5_C2_VAL GENMASK(14, 8)
66 #define MT_XO_CTRL6_C2_CTRL GENMASK(14, 8)
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/linux/drivers/net/wireless/ath/ath11k/
H A Dhal_desc.h11 #define BUFFER_ADDR_INFO0_ADDR GENMASK(31, 0)
13 #define BUFFER_ADDR_INFO1_ADDR GENMASK(7, 0)
14 #define BUFFER_ADDR_INFO1_RET_BUF_MGR GENMASK(10, 8)
15 #define BUFFER_ADDR_INFO1_SW_COOKIE GENMASK(31, 11)
476 #define HAL_TLV_HDR_TAG GENMASK(9, 1)
477 #define HAL_TLV_HDR_LEN GENMASK(25, 10)
478 #define HAL_TLV_USR_ID GENMASK(31, 26)
487 #define RX_MPDU_DESC_INFO0_MSDU_COUNT GENMASK(7, 0)
488 #define RX_MPDU_DESC_INFO0_SEQ_NUM GENMASK(19, 8)
501 #define RX_MPDU_DESC_META_DATA_PEER_ID GENMASK(15, 0)
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/linux/drivers/staging/media/sunxi/sun6i-isp/
H A Dsun6i_isp_reg.h21 #define SUN6I_ISP_FE_CFG_SRC0_MODE(v) (((v) << 8) & GENMASK(9, 8))
22 #define SUN6I_ISP_FE_CFG_SRC1_MODE(v) (((v) << 16) & GENMASK(17, 16))
33 #define SUN6I_ISP_FE_CTRL_OUTPUT_SPEED_CTRL(v) (((v) << 16) & GENMASK(17, 16))
104 #define SUN6I_ISP_MODE_INPUT_FMT(v) ((v) & GENMASK(2, 0))
105 #define SUN6I_ISP_MODE_INPUT_YUV_SEQ(v) (((v) << 3) & GENMASK(4, 3))
108 #define SUN6I_ISP_MODE_HIST(v) (((v) << 20) & GENMASK(21, 20))
123 #define SUN6I_ISP_IN_CFG_STRIDE_DIV16(v) ((v) & GENMASK(10, 0))
133 #define SUN6I_ISP_AE_CFG_LOW_BRI_TH(v) ((v) & GENMASK(11, 0))
134 #define SUN6I_ISP_AE_CFG_HORZ_NUM(v) (((v) << 12) & GENMASK(15, 12))
135 #define SUN6I_ISP_AE_CFG_HIGH_BRI_TH(v) (((v) << 16) & GENMASK(27, 16))
[all …]
/linux/drivers/mmc/host/
H A Dmeson-mx-sdhc.h14 #define MESON_SDHC_SEND_CMD_INDEX GENMASK(5, 0)
22 #define MESON_SDHC_SEND_TOTAL_PACK GENMASK(31, 16)
25 #define MESON_SDHC_CTRL_DAT_TYPE GENMASK(1, 0)
28 #define MESON_SDHC_CTRL_PACK_LEN GENMASK(12, 4)
29 #define MESON_SDHC_CTRL_RX_TIMEOUT GENMASK(19, 13)
30 #define MESON_SDHC_CTRL_RX_PERIOD GENMASK(23, 20)
31 #define MESON_SDHC_CTRL_RX_ENDIAN GENMASK(26, 24)
34 #define MESON_SDHC_CTRL_TX_ENDIAN GENMASK(31, 29)
38 #define MESON_SDHC_STAT_DAT3_0 GENMASK(4, 1)
40 #define MESON_SDHC_STAT_RXFIFO_CNT GENMASK(12, 6)
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