Lines Matching refs:GENMASK
17 #define DEV_CLOCK_CFG_LINK_SPEED(x) ((x) & GENMASK(1, 0))
18 #define DEV_CLOCK_CFG_LINK_SPEED_M GENMASK(1, 0)
27 #define DEV_EEE_CFG_EEE_TIMER_AGE(x) (((x) << 15) & GENMASK(21, 15))
28 #define DEV_EEE_CFG_EEE_TIMER_AGE_M GENMASK(21, 15)
29 #define DEV_EEE_CFG_EEE_TIMER_AGE_X(x) (((x) & GENMASK(21, 15)) >> 15)
30 #define DEV_EEE_CFG_EEE_TIMER_WAKEUP(x) (((x) << 8) & GENMASK(14, 8))
31 #define DEV_EEE_CFG_EEE_TIMER_WAKEUP_M GENMASK(14, 8)
32 #define DEV_EEE_CFG_EEE_TIMER_WAKEUP_X(x) (((x) & GENMASK(14, 8)) >> 8)
33 #define DEV_EEE_CFG_EEE_TIMER_HOLDOFF(x) (((x) << 1) & GENMASK(7, 1))
34 #define DEV_EEE_CFG_EEE_TIMER_HOLDOFF_M GENMASK(7, 1)
35 #define DEV_EEE_CFG_EEE_TIMER_HOLDOFF_X(x) (((x) & GENMASK(7, 1)) >> 1)
38 #define DEV_PTP_PREDICT_CFG_PTP_PHY_PREDICT_CFG(x) (((x) << 4) & GENMASK(11, 4))
39 #define DEV_PTP_PREDICT_CFG_PTP_PHY_PREDICT_CFG_M GENMASK(11, 4)
40 #define DEV_PTP_PREDICT_CFG_PTP_PHY_PREDICT_CFG_X(x) (((x) & GENMASK(11, 4)) >> 4)
41 #define DEV_PTP_PREDICT_CFG_PTP_PHASE_PREDICT_CFG(x) ((x) & GENMASK(3, 0))
42 #define DEV_PTP_PREDICT_CFG_PTP_PHASE_PREDICT_CFG_M GENMASK(3, 0)
51 #define DEV_MAC_TAGS_CFG_TAG_ID(x) (((x) << 16) & GENMASK(31, 16))
52 #define DEV_MAC_TAGS_CFG_TAG_ID_M GENMASK(31, 16)
53 #define DEV_MAC_TAGS_CFG_TAG_ID_X(x) (((x) & GENMASK(31, 16)) >> 16)
62 #define DEV_MAC_IFG_CFG_TX_IFG(x) (((x) << 8) & GENMASK(12, 8))
63 #define DEV_MAC_IFG_CFG_TX_IFG_M GENMASK(12, 8)
64 #define DEV_MAC_IFG_CFG_TX_IFG_X(x) (((x) & GENMASK(12, 8)) >> 8)
65 #define DEV_MAC_IFG_CFG_RX_IFG2(x) (((x) << 4) & GENMASK(7, 4))
66 #define DEV_MAC_IFG_CFG_RX_IFG2_M GENMASK(7, 4)
67 #define DEV_MAC_IFG_CFG_RX_IFG2_X(x) (((x) & GENMASK(7, 4)) >> 4)
68 #define DEV_MAC_IFG_CFG_RX_IFG1(x) ((x) & GENMASK(3, 0))
69 #define DEV_MAC_IFG_CFG_RX_IFG1_M GENMASK(3, 0)
74 #define DEV_MAC_HDX_CFG_SEED(x) (((x) << 16) & GENMASK(23, 16))
75 #define DEV_MAC_HDX_CFG_SEED_M GENMASK(23, 16)
76 #define DEV_MAC_HDX_CFG_SEED_X(x) (((x) & GENMASK(23, 16)) >> 16)
79 #define DEV_MAC_HDX_CFG_LATE_COL_POS(x) ((x) & GENMASK(6, 0))
80 #define DEV_MAC_HDX_CFG_LATE_COL_POS_M GENMASK(6, 0)
101 #define DEV_MM_CONFIG_VERIF_CONFIG_PRM_VERIFY_TIME(x) (((x) << 4) & GENMASK(11, 4))
102 #define DEV_MM_CONFIG_VERIF_CONFIG_PRM_VERIFY_TIME_M GENMASK(11, 4)
103 #define DEV_MM_CONFIG_VERIF_CONFIG_PRM_VERIFY_TIME_X(x) (((x) & GENMASK(11, 4)) >> 4)
104 #define DEV_MM_CONFIG_VERIF_CONFIG_VERIF_TIMER_UNITS(x) (((x) << 12) & GENMASK(13, 12))
105 #define DEV_MM_CONFIG_VERIF_CONFIG_VERIF_TIMER_UNITS_M GENMASK(13, 12)
106 #define DEV_MM_CONFIG_VERIF_CONFIG_VERIF_TIMER_UNITS_X(x) (((x) & GENMASK(13, 12)) >> 12)
110 #define DEV_MM_STAT_MM_STATUS_PRMPT_VERIFY_STATE(x) (((x) << 8) & GENMASK(10, 8))
111 #define DEV_MM_STAT_MM_STATUS_PRMPT_VERIFY_STATE_M GENMASK(10, 8)
112 #define DEV_MM_STAT_MM_STATUS_PRMPT_VERIFY_STATE_X(x) (((x) & GENMASK(10, 8)) >> 8)
130 #define PCS1G_ANEG_CFG_ADV_ABILITY(x) (((x) << 16) & GENMASK(31, 16))
131 #define PCS1G_ANEG_CFG_ADV_ABILITY_M GENMASK(31, 16)
132 #define PCS1G_ANEG_CFG_ADV_ABILITY_X(x) (((x) & GENMASK(31, 16)) >> 16)
137 #define PCS1G_ANEG_NP_CFG_NP_TX(x) (((x) << 16) & GENMASK(31, 16))
138 #define PCS1G_ANEG_NP_CFG_NP_TX_M GENMASK(31, 16)
139 #define PCS1G_ANEG_NP_CFG_NP_TX_X(x) (((x) & GENMASK(31, 16)) >> 16)
150 #define PCS1G_ANEG_STATUS_LP_ADV_ABILITY(x) (((x) << 16) & GENMASK(31, 16))
151 #define PCS1G_ANEG_STATUS_LP_ADV_ABILITY_M GENMASK(31, 16)
152 #define PCS1G_ANEG_STATUS_LP_ADV_ABILITY_X(x) (((x) & GENMASK(31, 16)) >> 16)
157 #define PCS1G_LINK_STATUS_DELAY_VAR(x) (((x) << 12) & GENMASK(15, 12))
158 #define PCS1G_LINK_STATUS_DELAY_VAR_M GENMASK(15, 12)
159 #define PCS1G_LINK_STATUS_DELAY_VAR_X(x) (((x) & GENMASK(15, 12)) >> 12)
170 #define PCS1G_LPI_CFG_LPI_RX_WTIM(x) (((x) << 4) & GENMASK(5, 4))
171 #define PCS1G_LPI_CFG_LPI_RX_WTIM_M GENMASK(5, 4)
172 #define PCS1G_LPI_CFG_LPI_RX_WTIM_X(x) (((x) & GENMASK(5, 4)) >> 4)
183 #define PCS1G_TSTPAT_STATUS_JTP_ERR_CNT(x) (((x) << 8) & GENMASK(15, 8))
184 #define PCS1G_TSTPAT_STATUS_JTP_ERR_CNT_M GENMASK(15, 8)
185 #define PCS1G_TSTPAT_STATUS_JTP_ERR_CNT_X(x) (((x) & GENMASK(15, 8)) >> 8)
194 #define DEV_PCS_FX100_CFG_RXBITSEL(x) (((x) << 12) & GENMASK(15, 12))
195 #define DEV_PCS_FX100_CFG_RXBITSEL_M GENMASK(15, 12)
196 #define DEV_PCS_FX100_CFG_RXBITSEL_X(x) (((x) & GENMASK(15, 12)) >> 12)
197 #define DEV_PCS_FX100_CFG_SIGDET_CFG(x) (((x) << 9) & GENMASK(10, 9))
198 #define DEV_PCS_FX100_CFG_SIGDET_CFG_M GENMASK(10, 9)
199 #define DEV_PCS_FX100_CFG_SIGDET_CFG_X(x) (((x) & GENMASK(10, 9)) >> 9)
201 #define DEV_PCS_FX100_CFG_LINKHYSTTIMER(x) (((x) << 4) & GENMASK(7, 4))
202 #define DEV_PCS_FX100_CFG_LINKHYSTTIMER_M GENMASK(7, 4)
203 #define DEV_PCS_FX100_CFG_LINKHYSTTIMER_X(x) (((x) & GENMASK(7, 4)) >> 4)
209 #define DEV_PCS_FX100_STATUS_EDGE_POS_PTP(x) (((x) << 8) & GENMASK(11, 8))
210 #define DEV_PCS_FX100_STATUS_EDGE_POS_PTP_M GENMASK(11, 8)
211 #define DEV_PCS_FX100_STATUS_EDGE_POS_PTP_X(x) (((x) & GENMASK(11, 8)) >> 8)