Searched refs:GCR (Results 1 – 11 of 11) sorted by relevance
123 writel(readl(ac97_reg_base + GCR) | (GCR_WARM_RST), ac97_reg_base + GCR); in pxa_ac97_warm_pxa25x()128 …writel(readl(ac97_reg_base + GCR) & ( GCR_COLD_RST), ac97_reg_base + GCR); /* clear everything bu… in pxa_ac97_cold_pxa25x()129 writel(readl(ac97_reg_base + GCR) & (~GCR_COLD_RST), ac97_reg_base + GCR); /* then assert nCRST */ in pxa_ac97_cold_pxa25x()133 writel(GCR_COLD_RST, ac97_reg_base + GCR); in pxa_ac97_cold_pxa25x()145 writel(readl(ac97_reg_base + GCR) | (GCR_WARM_RST), ac97_reg_base + GCR); in pxa_ac97_warm_pxa27x()152 …writel(readl(ac97_reg_base + GCR) & ( GCR_COLD_RST), ac97_reg_base + GCR); /* clear everything bu… in pxa_ac97_cold_pxa27x()153 writel(readl(ac97_reg_base + GCR) & (~GCR_COLD_RST), ac97_reg_base + GCR); /* then assert nCRST */ in pxa_ac97_cold_pxa27x()161 writel(GCR_COLD_RST | GCR_WARM_RST, ac97_reg_base + GCR); in pxa_ac97_cold_pxa27x()171 writel(readl(ac97_reg_base + GCR) | (GCR_WARM_RST), ac97_reg_base + GCR); in pxa_ac97_warm_pxa3xx()177 writel(0, ac97_reg_base + GCR); in pxa_ac97_cold_pxa3xx()[all …]
21 #define GCR (0x000C) /* Global Control Register */ macro
176 u32 GCR; /* Global Control Register */ member206 .GCR = 0x0,232 .GCR = 0x0,363 lvds_set(lvds, phy->base + phy->ofs.GCR, lvds_gcr); in lvds_pll_enable()573 lvds_set(lvds, phy->base + phy->ofs.GCR, PHY_GCR_DIV_RSTN | PHY_GCR_RSTZ); in lvds_pixel_clk_enable()587 lvds_set(lvds, phy->base + phy->ofs.GCR, PHY_GCR_DIV_RSTN | PHY_GCR_RSTZ); in lvds_pixel_clk_enable()612 lvds_clear(lvds, lvds->primary->base + lvds->primary->ofs.GCR, in lvds_pixel_clk_disable()616 lvds_clear(lvds, lvds->primary->base + lvds->primary->ofs.GCR, in lvds_pixel_clk_disable()621 lvds_clear(lvds, lvds->secondary->base + lvds->secondary->ofs.GCR, in lvds_pixel_clk_disable()625 lvds_clear(lvds, lvds->secondary->base + lvds->secondary->ofs.GCR, in lvds_pixel_clk_disable()
37 [GCR] = { 0x0078, 0x00, OMAP_DMA_REG_32BIT },
1114 reg_data = er32(GCR); in e1000_init_hw_82571()1116 ew32(GCR, reg_data); in e1000_init_hw_82571()1246 reg = er32(GCR); in e1000_initialize_hw_bits_82571()1248 ew32(GCR, reg); in e1000_initialize_hw_bits_82571()
1690 gcr = er32(GCR); in e1000e_set_pcie_no_snoop()1693 ew32(GCR, gcr); in e1000e_set_pcie_no_snoop()
140 GCR, GSCR, GRST1, HW_ID, enumerator
36 [GCR] = { 0x0400, 0x00, OMAP_DMA_REG_16BIT },
3081 u8 GCR; in velocity_set_wol() local3082 GCR = readb(®s->CHIPGCR); in velocity_set_wol()3083 GCR = (GCR & ~CHIPGCR_FCGMII) | CHIPGCR_FCFDX; in velocity_set_wol()3084 writeb(GCR, ®s->CHIPGCR); in velocity_set_wol()
1580 od->context.gcr = omap_dma_glbl_read(od, GCR); in omap_dma_context_save()1587 omap_dma_glbl_write(od, GCR, od->context.gcr); in omap_dma_context_restore()1643 omap_dma_glbl_write(od, GCR, val); in omap_dma_init_gcr()
41 #define GCR 0x004C /* Global control register */ macro