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Searched refs:GATE (Results 1 – 25 of 28) sorted by relevance

12

/linux/drivers/clk/samsung/
H A Dclk-fsd.c261 GATE(0, "cmu_cis0_clkgate", "mout_cmu_cis0_clkmux", GAT_CMU_CIS0_CLKGATE, 21,
263 GATE(0, "cmu_cis1_clkgate", "mout_cmu_cis1_clkmux", GAT_CMU_CIS1_CLKGATE, 21,
265 GATE(0, "cmu_cis2_clkgate", "mout_cmu_cis2_clkmux", GAT_CMU_CIS2_CLKGATE, 21,
267 GATE(CMU_CPUCL_SWITCH_GATE, "cmu_cpucl_switch_gate", "mout_cmu_cpucl_switchmux",
269 GATE(GAT_CMU_FSYS0_SHARED0DIV4, "cmu_fsys0_shared0div4_gate", "dout_cmu_pll_shared0_div4",
271 GATE(0, "cmu_fsys0_shared1div4_clk", "dout_cmu_pll_shared1_div3",
273 GATE(0, "cmu_fsys0_shared1div4_gate", "dout_cmu_pll_shared1_div4",
275 GATE(0, "cmu_fsys1_shared0div4_gate", "mout_cmu_fsys1_aclk_mux",
277 GATE(0, "cmu_fsys1_shared1div4_gate", "dout_cmu_fsys1_shared0div4",
279 GATE(0, "cmu_imem_aclk_gate", "dout_cmu_pll_shared1_div9", GAT_CMU_IMEM_ACLK_GATE, 21,
[all …]
H A Dclk-exynos990.c1025 GATE(CLK_GOUT_CMU_APM_BUS, "gout_cmu_apm_bus", "mout_cmu_apm_bus",
1027 GATE(CLK_GOUT_CMU_AUD_CPU, "gout_cmu_aud_cpu", "mout_cmu_aud_cpu",
1029 GATE(CLK_GOUT_CMU_BUS0_BUS, "gout_cmu_bus0_bus", "mout_cmu_bus0_bus",
1031 GATE(CLK_GOUT_CMU_BUS1_BUS, "gout_cmu_bus1_bus", "mout_cmu_bus1_bus",
1033 GATE(CLK_GOUT_CMU_BUS1_SSS, "gout_cmu_bus1_sss", "mout_cmu_bus1_sss",
1035 GATE(CLK_GOUT_CMU_CIS_CLK0, "gout_cmu_cis_clk0", "mout_cmu_cis_clk0",
1037 GATE(CLK_GOUT_CMU_CIS_CLK1, "gout_cmu_cis_clk1", "mout_cmu_cis_clk1",
1039 GATE(CLK_GOUT_CMU_CIS_CLK2, "gout_cmu_cis_clk2", "mout_cmu_cis_clk2",
1041 GATE(CLK_GOUT_CMU_CIS_CLK3, "gout_cmu_cis_clk3", "mout_cmu_cis_clk3",
1043 GATE(CLK_GOUT_CMU_CIS_CLK4, "gout_cmu_cis_clk4", "mout_cmu_cis_clk4",
[all …]
H A Dclk-artpec8.c527 GATE(CLK_GOUT_CPUCL_CLUSTER_CPU, "clk_con_gat_clk_cluster_cpu",
530 GATE(CLK_GOUT_CPUCL_SHORTSTOP, "clk_con_gat_clk_cpucl_shortstop",
533 GATE(CLK_GOUT_CPUCL_CSSYS_IPCLKPORT_PCLKDBG, "cssys_ipclkport_pclkdbg",
536 GATE(CLK_GOUT_CPUCL_CSSYS_IPCLKPORT_ATCLK, "cssys_ipclkport_atclk",
713 GATE(CLK_GOUT_FSYS_PCIE_PHY_REFCLK_IN, "pcie_sub_ctrl_inst_0_phy_refclk_in",
716 GATE(CLK_GOUT_FSYS_EQOS_TOP_IPCLKPORT_I_RGMII_TXCLK_2P5,
719 GATE(CLK_GOUT_FSYS_EQOS_TOP_IPCLKPORT_ACLK_I, "eqos_top_ipclkport_aclk_i",
721 GATE(CLK_GOUT_FSYS_EQOS_TOP_IPCLKPORT_CLK_CSR_I, "eqos_top_ipclkport_clk_csr_i",
723 GATE(CLK_GOUT_FSYS_PIPE_PAL_INST_0_I_APB_PCLK, "pipe_pal_inst_0_i_apb_pclk",
725 GATE(CLK_GOUT_FSYS_QSPI_IPCLKPORT_HCLK, "qspi_ipclkport_hclk",
[all …]
/linux/drivers/clk/rockchip/
H A Dclk-rk3368.c284 GATE(0, "apllb_core", "apllb", CLK_IGNORE_UNUSED,
286 GATE(0, "gpllb_core", "gpll", CLK_IGNORE_UNUSED,
289 GATE(0, "aplll_core", "aplll", CLK_IGNORE_UNUSED,
291 GATE(0, "gplll_core", "gpll", CLK_IGNORE_UNUSED,
308 GATE(0, "apllb_cs", "apllb", CLK_IGNORE_UNUSED,
310 GATE(0, "aplll_cs", "aplll", CLK_IGNORE_UNUSED,
312 GATE(0, "gpll_cs", "gpll", CLK_IGNORE_UNUSED,
323 GATE(SCLK_PVTM_CORE, "sclk_pvtm_core", "xin24m", 0, RK3368_CLKGATE_CON(7), 10, GFLAGS),
325 GATE(0, "dpll_ddr", "dpll", CLK_IGNORE_UNUSED,
327 GATE(0, "gpll_ddr", "gpll", 0,
[all …]
H A Dclk-rv1126b.c305 GATE(CLKOUT_PDM, "clkout_pdm", "clkout_pdm_src", 0,
346 GATE(HCLK_RKNN, "hclk_rknn", "clk_gpll_div8", CLK_IS_CRITICAL,
348 GATE(PCLK_NPU_ROOT, "pclk_npu_root", "clk_cpll_div10", CLK_IS_CRITICAL,
353 GATE(HCLK_VEPU_ROOT, "hclk_vepu_root", "clk_gpll_div8", CLK_IS_CRITICAL,
355 GATE(PCLK_VEPU_ROOT, "pclk_vepu_root", "clk_cpll_div10", 0,
366 GATE(HCLK_VI_ROOT, "hclk_vi_root", "clk_gpll_div8", CLK_IS_CRITICAL,
368 GATE(PCLK_VI_ROOT, "pclk_vi_root", "clk_cpll_div10", CLK_IS_CRITICAL,
382 GATE(HCLK_VDO_ROOT, "hclk_vdo_root", "clk_gpll_div8", CLK_IS_CRITICAL,
384 GATE(PCLK_VDO_ROOT, "pclk_vdo_root", "clk_cpll_div10", CLK_IS_CRITICAL,
392 GATE(DCLK_DECOM_SRC, "dclk_decom_src", "clk_gpll_div3", 0,
[all …]
H A Dclk-rk3399.c406 GATE(SCLK_USB2PHY0_REF, "clk_usb2phy0_ref", "xin24m", CLK_IGNORE_UNUSED,
408 GATE(SCLK_USB2PHY1_REF, "clk_usb2phy1_ref", "xin24m", CLK_IGNORE_UNUSED,
411 GATE(0, "clk_usbphy0_480m_src", "clk_usbphy0_480m", 0,
413 GATE(0, "clk_usbphy1_480m_src", "clk_usbphy1_480m", 0,
428 GATE(ACLK_USB3_NOC, "aclk_usb3_noc", "aclk_usb3", CLK_IGNORE_UNUSED,
430 GATE(ACLK_USB3OTG0, "aclk_usb3otg0", "aclk_usb3", 0,
432 GATE(ACLK_USB3OTG1, "aclk_usb3otg1", "aclk_usb3", 0,
434 GATE(ACLK_USB3_RKSOC_AXI_PERF, "aclk_usb3_rksoc_axi_perf", "aclk_usb3", 0,
436 GATE(ACLK_USB3_GRF, "aclk_usb3_grf", "aclk_usb3", 0,
439 GATE(SCLK_USB3OTG0_REF, "clk_usb3otg0_ref", "xin24m", 0,
[all …]
H A Dclk-rk3228.c220 GATE(0, "apll_ddr", "apll", CLK_IGNORE_UNUSED,
222 GATE(0, "dpll_ddr", "dpll", CLK_IGNORE_UNUSED,
224 GATE(0, "gpll_ddr", "gpll", CLK_IGNORE_UNUSED,
229 GATE(0, "ddrc", "ddrphy_pre", CLK_IGNORE_UNUSED,
235 GATE(0, "dpll_core", "dpll", CLK_IGNORE_UNUSED,
237 GATE(0, "apll_core", "apll", CLK_IGNORE_UNUSED,
239 GATE(0, "gpll_core", "gpll", CLK_IGNORE_UNUSED,
257 GATE(0, "hdmiphy_aclk_cpu", "hdmiphy", CLK_IGNORE_UNUSED,
259 GATE(0, "gpll_aclk_cpu", "gpll", CLK_IGNORE_UNUSED,
261 GATE(0, "cpll_aclk_cpu", "cpll", CLK_IGNORE_UNUSED,
[all …]
H A Dclk-rk3328.c286 GATE(0, "apll_core", "apll", CLK_IGNORE_UNUSED,
288 GATE(0, "gpll_core", "gpll", CLK_IGNORE_UNUSED,
290 GATE(0, "dpll_core", "dpll", CLK_IGNORE_UNUSED,
292 GATE(0, "npll_core", "npll", CLK_IGNORE_UNUSED,
300 GATE(0, "aclk_core_niu", "aclk_core", 0,
302 GATE(0, "aclk_gic400", "aclk_core", CLK_IGNORE_UNUSED,
305 GATE(0, "clk_jtag", "jtag_clkin", CLK_IGNORE_UNUSED,
312 GATE(ACLK_GPU, "aclk_gpu", "aclk_gpu_pre", CLK_SET_RATE_PARENT,
314 GATE(0, "aclk_gpu_niu", "aclk_gpu_pre", 0,
321 GATE(0, "clk_ddrmsch", "clk_ddr", CLK_IGNORE_UNUSED,
[all …]
H A Dclk-rv1108.c201 GATE(0, "dpll_core", "dpll", CLK_IGNORE_UNUSED,
203 GATE(0, "apll_core", "apll", CLK_IGNORE_UNUSED,
205 GATE(0, "gpll_core", "gpll", CLK_IGNORE_UNUSED,
213 GATE(ACLK_CORE, "aclk_core", "aclkenm_core", CLK_IGNORE_UNUSED,
215 GATE(0, "pclk_dbg", "pclken_dbg", CLK_IGNORE_UNUSED,
227 GATE(ACLK_RKVENC, "aclk_rkvenc", "aclk_rkvenc_pre", 0,
229 GATE(HCLK_RKVENC, "hclk_rkvenc", "hclk_rkvenc_pre", 0,
231 GATE(0, "aclk_rkvenc_niu", "aclk_rkvenc_pre", CLK_IGNORE_UNUSED,
233 GATE(0, "hclk_rkvenc_niu", "hclk_rkvenc_pre", CLK_IGNORE_UNUSED,
252 GATE(ACLK_RKVDEC, "aclk_rkvdec", "aclk_rkvdec_pre", 0,
[all …]
H A Dclk-rk3288.c287 GATE(0, "apll_core", "apll", CLK_IGNORE_UNUSED,
289 GATE(0, "gpll_core", "gpll", CLK_IGNORE_UNUSED,
319 GATE(0, "pclk_dbg", "pclk_dbg_pre", 0,
321 GATE(0, "cs_dbg", "pclk_dbg_pre", CLK_IGNORE_UNUSED,
323 GATE(0, "pclk_core_niu", "pclk_dbg_pre", 0,
326 GATE(0, "dpll_ddr", "dpll", CLK_IGNORE_UNUSED,
328 GATE(0, "gpll_ddr", "gpll", 0,
334 GATE(0, "gpll_aclk_cpu", "gpll", CLK_IGNORE_UNUSED,
336 GATE(0, "cpll_aclk_cpu", "cpll", CLK_IGNORE_UNUSED,
342 GATE(ACLK_CPU, "aclk_cpu", "aclk_cpu_pre", CLK_IGNORE_UNUSED,
[all …]
H A Dclk-rv1126.c284 GATE(CLK_WIFI_OSC0, "clk_wifi_osc0", "xin24m", 0,
289 GATE(PCLK_PMU, "pclk_pmu", "pclk_pdpmu", CLK_IGNORE_UNUSED,
292 GATE(PCLK_UART1, "pclk_uart1", "pclk_pdpmu", 0,
302 GATE(SCLK_UART1, "sclk_uart1", "sclk_uart1_mux", 0,
305 GATE(PCLK_I2C0, "pclk_i2c0", "pclk_pdpmu", 0,
310 GATE(PCLK_I2C2, "pclk_i2c2", "pclk_pdpmu", 0,
316 GATE(CLK_CAPTURE_PWM0, "clk_capture_pwm0", "xin24m", 0,
318 GATE(PCLK_PWM0, "pclk_pwm0", "pclk_pdpmu", 0,
323 GATE(CLK_CAPTURE_PWM1, "clk_capture_pwm1", "xin24m", 0,
325 GATE(PCLK_PWM1, "pclk_pwm1", "pclk_pdpmu", 0,
[all …]
H A Dclk-rk3528.c310 GATE(SCLK_UART0, "sclk_uart0", "clk_uart0", 0,
320 GATE(SCLK_UART1, "sclk_uart1", "clk_uart1", 0,
330 GATE(SCLK_UART2, "sclk_uart2", "clk_uart2", 0,
340 GATE(SCLK_UART3, "sclk_uart3", "clk_uart3", 0,
350 GATE(SCLK_UART4, "sclk_uart4", "clk_uart4", 0,
360 GATE(SCLK_UART5, "sclk_uart5", "clk_uart5", 0,
370 GATE(SCLK_UART6, "sclk_uart6", "clk_uart6", 0,
380 GATE(SCLK_UART7, "sclk_uart7", "clk_uart7", 0,
390 GATE(MCLK_I2S0_2CH_SAI_SRC, "mclk_i2s0_2ch_sai_src", "mclk_i2s0_2ch_sai_src_pre", 0,
400 GATE(MCLK_I2S1_8CH_SAI_SRC, "mclk_i2s1_8ch_sai_src", "mclk_i2s1_8ch_sai_src_pre", 0,
[all …]
H A Dclk-rk3506.c175 GATE(XIN24M_GATE, "xin24m_gate", "xin24m", CLK_IS_CRITICAL,
177 GATE(CLK_GPLL_GATE, "clk_gpll_gate", "gpll", CLK_IS_CRITICAL,
179 GATE(CLK_V0PLL_GATE, "clk_v0pll_gate", "v0pll", CLK_IS_CRITICAL,
181 GATE(CLK_V1PLL_GATE, "clk_v1pll_gate", "v1pll", 0,
239 GATE(CLK_REF_USBPHY_TOP, "clk_ref_usbphy_top", "xin24m", 0,
241 GATE(CLK_REF_DPHY_TOP, "clk_ref_dphy_top", "xin24m", 0,
253 GATE(PCLK_DBG, "pclk_dbg", "pclk_core_root", CLK_IGNORE_UNUSED,
255 GATE(PCLK_CORE_GRF, "pclk_core_grf", "pclk_core_root", CLK_IGNORE_UNUSED,
257 GATE(PCLK_CORE_CRU, "pclk_core_cru", "pclk_core_root", CLK_IGNORE_UNUSED,
259 GATE(CLK_CORE_EMA_DETECT, "clk_core_ema_detect", "xin24m_gate", CLK_IGNORE_UNUSED,
[all …]
H A Dclk-rk3588.c785 GATE(PCLK_MIPI_DCPHY0, "pclk_mipi_dcphy0", "pclk_top_root", 0,
787 GATE(PCLK_MIPI_DCPHY1, "pclk_mipi_dcphy1", "pclk_top_root", 0,
789 GATE(PCLK_CSIPHY0, "pclk_csiphy0", "pclk_top_root", 0,
791 GATE(PCLK_CSIPHY1, "pclk_csiphy1", "pclk_top_root", 0,
793 GATE(PCLK_CRU, "pclk_cru", "pclk_top_root", CLK_IS_CRITICAL,
801 GATE(PCLK_BIGCORE0_PVTM, "pclk_bigcore0_pvtm", "pclk_bigcore0_root", 0,
803 GATE(CLK_BIGCORE0_PVTM, "clk_bigcore0_pvtm", "xin24m", 0,
805 GATE(CLK_CORE_BIGCORE0_PVTM, "clk_core_bigcore0_pvtm", "armclk_b01", 0,
813 GATE(PCLK_BIGCORE1_PVTM, "pclk_bigcore1_pvtm", "pclk_bigcore1_root", 0,
815 GATE(CLK_BIGCORE1_PVTM, "clk_bigcore1_pvtm", "xin24m", 0,
[all …]
H A Dclk-px30.c278 GATE(0, "apll_core", "apll", CLK_IGNORE_UNUSED,
280 GATE(0, "gpll_core", "gpll", CLK_IGNORE_UNUSED,
288 GATE(0, "aclk_core_niu", "aclk_core", CLK_IGNORE_UNUSED,
290 GATE(0, "aclk_core_prf", "aclk_core", CLK_IGNORE_UNUSED,
292 GATE(0, "pclk_dbg_niu", "pclk_dbg", CLK_IGNORE_UNUSED,
294 GATE(0, "pclk_core_dbg", "pclk_dbg", CLK_IGNORE_UNUSED,
296 GATE(0, "pclk_core_grf", "pclk_dbg", CLK_IGNORE_UNUSED,
299 GATE(0, "clk_jtag", "jtag_clkin", CLK_IGNORE_UNUSED,
301 GATE(SCLK_PVTM, "clk_pvtm", "xin24m", 0,
320 GATE(0, "aclk_gpu_niu", "aclk_gpu", CLK_IGNORE_UNUSED,
[all …]
H A Dclk-rk3128.c209 GATE(0, "dpll_ddr", "dpll", CLK_IGNORE_UNUSED,
211 GATE(0, "gpll_div2_ddr", "gpll_div2", CLK_IGNORE_UNUSED,
219 GATE(0, "apll_core", "apll", CLK_IGNORE_UNUSED,
221 GATE(0, "gpll_div2_core", "gpll_div2", CLK_IGNORE_UNUSED,
238 GATE(ACLK_CPU, "aclk_cpu", "aclk_cpu_src", 0,
288 GATE(ACLK_PERI, "aclk_peri", "clk_peri_src", 0,
291 GATE(SCLK_TIMER0, "sclk_timer0", "xin24m", 0,
293 GATE(SCLK_TIMER1, "sclk_timer1", "xin24m", 0,
295 GATE(SCLK_TIMER2, "sclk_timer2", "xin24m", 0,
297 GATE(SCLK_TIMER3, "sclk_timer3", "xin24m", 0,
[all …]
H A Dclk-rk3576.c540 GATE(CLK_GMAC0_RMII_CRU, "clk_gmac0_rmii_cru", "clk_cpll_div20", 0,
542 GATE(CLK_GMAC1_RMII_CRU, "clk_gmac1_rmii_cru", "clk_cpll_div20", 0,
544 GATE(CLK_OTPC_AUTO_RD_G, "clk_otpc_auto_rd_g", "xin24m", 0,
546 GATE(CLK_OTP_PHY_G, "clk_otp_phy_g", "xin24m", 0,
571 GATE(HCLK_CAN0, "hclk_can0", "hclk_bus_root", 0,
576 GATE(HCLK_CAN1, "hclk_can1", "hclk_bus_root", 0,
581 GATE(CLK_KEY_SHIFT, "clk_key_shift", "xin24m", CLK_IS_CRITICAL,
583 GATE(PCLK_I2C1, "pclk_i2c1", "pclk_bus_root", 0,
585 GATE(PCLK_I2C2, "pclk_i2c2", "pclk_bus_root", 0,
587 GATE(PCLK_I2C3, "pclk_i2c3", "pclk_bus_root", 0,
[all …]
H A Dclk-rk3568.c529 GATE(CLK_CORE_PVTM, "clk_core_pvtm", "xin24m", 0,
531 GATE(CLK_CORE_PVTM_CORE, "clk_core_pvtm_core", "armclk", 0,
533 GATE(CLK_CORE_PVTPLL, "clk_core_pvtpll", "armclk", CLK_IGNORE_UNUSED,
535 GATE(PCLK_CORE_PVTM, "pclk_core_pvtm", "pclk_core_pre", 0,
548 GATE(CLK_GPU, "clk_gpu", "clk_gpu_pre_mux", 0,
551 GATE(PCLK_GPU_PVTM, "pclk_gpu_pvtm", "pclk_gpu_pre", 0,
553 GATE(CLK_GPU_PVTM, "clk_gpu_pvtm", "xin24m", 0,
555 GATE(CLK_GPU_PVTM_CORE, "clk_gpu_pvtm_core", "clk_gpu_src", 0,
557 GATE(CLK_GPU_PVTPLL, "clk_gpu_pvtpll", "clk_gpu_src", CLK_IGNORE_UNUSED,
574 GATE(ACLK_NPU_PRE, "aclk_npu_pre", "clk_npu", 0,
[all …]
H A Dclk-rk3308.c292 GATE(0, "apll_core", "apll", CLK_IGNORE_UNUSED,
294 GATE(0, "vpll0_core", "vpll0", CLK_IGNORE_UNUSED,
296 GATE(0, "vpll1_core", "vpll1", CLK_IGNORE_UNUSED,
305 GATE(0, "clk_jtag", "jtag_clkin", CLK_IGNORE_UNUSED,
308 GATE(SCLK_PVTM_CORE, "clk_pvtm_core", "xin24m", 0,
321 GATE(PCLK_DDR, "pclk_ddr", "pclk_bus", CLK_IGNORE_UNUSED,
337 GATE(SCLK_UART0, "clk_uart0", "clk_uart0_mux", 0,
347 GATE(SCLK_UART1, "clk_uart1", "clk_uart1_mux", 0,
357 GATE(SCLK_UART2, "clk_uart2", "clk_uart2_mux", CLK_SET_RATE_PARENT,
367 GATE(SCLK_UART3, "clk_uart3", "clk_uart3_mux", 0,
[all …]
H A Dclk-rk3036.c175 GATE(0, "gpll_armclk", "gpll", CLK_IGNORE_UNUSED,
184 GATE(0, "dpll_ddr", "dpll", CLK_IGNORE_UNUSED,
186 GATE(0, "gpll_ddr", "gpll", CLK_IGNORE_UNUSED,
199 GATE(0, "dpll_cpu", "dpll", 0, RK2928_CLKGATE_CON(10), 8, GFLAGS),
200 GATE(0, "gpll_cpu", "gpll", 0, RK2928_CLKGATE_CON(0), 1, GFLAGS),
203 GATE(ACLK_CPU, "aclk_cpu", "aclk_cpu_src", CLK_IGNORE_UNUSED,
216 GATE(ACLK_PERI, "aclk_peri", "aclk_peri_src", 0,
220 GATE(PCLK_PERI, "pclk_peri", "pclk_peri_src", 0,
224 GATE(HCLK_PERI, "hclk_peri", "hclk_peri_src", 0,
319 GATE(SCLK_I2S, "sclk_i2s", "i2s_pre", CLK_SET_RATE_PARENT,
[all …]
/linux/drivers/clk/pistachio/
H A Dclk-pistachio.c19 GATE(CLK_MIPS, "mips", "mips_div", 0x104, 0),
20 GATE(CLK_AUDIO_IN, "audio_in", "audio_clk_in_gate", 0x104, 1),
21 GATE(CLK_AUDIO, "audio", "audio_div", 0x104, 2),
22 GATE(CLK_I2S, "i2s", "i2s_div", 0x104, 3),
23 GATE(CLK_SPDIF, "spdif", "spdif_div", 0x104, 4),
24 GATE(CLK_AUDIO_DAC, "audio_dac", "audio_dac_div", 0x104, 5),
25 GATE(CLK_RPU_V, "rpu_v", "rpu_v_div", 0x104, 6),
26 GATE(CLK_RPU_L, "rpu_l", "rpu_l_div", 0x104, 7),
27 GATE(CLK_RPU_SLEEP, "rpu_sleep", "rpu_sleep_div", 0x104, 8),
28 GATE(CLK_WIFI_PLL_GATE, "wifi_pll_gate", "wifi_pll_mux", 0x104, 9),
[all …]
H A Dclk.h19 #define GATE(_id, _name, _pname, _reg, _shift) \ macro
/linux/drivers/clk/bcm/
H A Dclk-kona.h46 #define gate_exists(gate) FLAG_TEST(gate, GATE, EXISTS)
47 #define gate_is_enabled(gate) FLAG_TEST(gate, GATE, ENABLED)
48 #define gate_is_hw_controllable(gate) FLAG_TEST(gate, GATE, HW)
49 #define gate_is_sw_controllable(gate) FLAG_TEST(gate, GATE, SW)
50 #define gate_is_sw_managed(gate) FLAG_TEST(gate, GATE, SW_MANAGED)
51 #define gate_is_no_disable(gate) FLAG_TEST(gate, GATE, NO_DISABLE)
53 #define gate_flip_enabled(gate) FLAG_FLIP(gate, GATE, ENABLED)
157 .flags = FLAG(GATE, HW)|FLAG(GATE, SW)| \
158 FLAG(GATE, SW_MANAGED)|FLAG(GATE, ENABLED)| \
159 FLAG(GATE, EXISTS), \
[all …]
/linux/drivers/clk/tegra/
H A Dclk-tegra-periph.c229 #define GATE(_name, _parent_name, \ macro
773 GATE("rtc", "clk_32k", 4, TEGRA_PERIPH_ON_APB | TEGRA_PERIPH_NO_RESET, tegra_clk_rtc, 0),
774 GATE("timer", "clk_m", 5, 0, tegra_clk_timer, CLK_IS_CRITICAL),
775 GATE("isp", "clk_m", 23, 0, tegra_clk_isp, 0),
776 GATE("vcp", "clk_m", 29, 0, tegra_clk_vcp, 0),
777 GATE("ahbdma", "hclk", 33, 0, tegra_clk_ahbdma, 0),
778 GATE("apbdma", "pclk", 34, 0, tegra_clk_apbdma, 0),
779 GATE("kbc", "clk_32k", 36, TEGRA_PERIPH_ON_APB | TEGRA_PERIPH_NO_RESET, tegra_clk_kbc, 0),
780 GATE("fuse", "clk_m", 39, TEGRA_PERIPH_ON_APB, tegra_clk_fuse, 0),
781 GATE("fuse_burn", "clk_m", 39, TEGRA_PERIPH_ON_APB, tegra_clk_fuse_burn, 0),
[all …]
/linux/drivers/clk/ralink/
H A Dclk-mt7621.c62 #define GATE(_id, _name, _pname, _shift) \ macro
71 GATE(MT7621_CLK_HSDMA, "hsdma", "150m", BIT(5)),
72 GATE(MT7621_CLK_FE, "fe", "250m", BIT(6)),
73 GATE(MT7621_CLK_SP_DIVTX, "sp_divtx", "270m", BIT(7)),
74 GATE(MT7621_CLK_TIMER, "timer", "50m", BIT(8)),
75 GATE(MT7621_CLK_PCM, "pcm", "270m", BIT(11)),
76 GATE(MT7621_CLK_PIO, "pio", "50m", BIT(13)),
77 GATE(MT7621_CLK_GDMA, "gdma", "bus", BIT(14)),
78 GATE(MT7621_CLK_NAND, "nand", "125m", BIT(15)),
79 GATE(MT7621_CLK_I2C, "i2c", "50m", BIT(16)),
[all …]

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