Searched refs:EVENT_TYPE (Results 1 – 9 of 9) sorted by relevance
227 #define EVENT_TYPE(x) ((x) << 0) macro
1558 ib.ptr[ib.length_dw++] = EVENT_TYPE(7) | EVENT_INDEX(4); in gfx_v8_0_do_edc_gpr_workarounds()1584 ib.ptr[ib.length_dw++] = EVENT_TYPE(7) | EVENT_INDEX(4); in gfx_v8_0_do_edc_gpr_workarounds()1610 ib.ptr[ib.length_dw++] = EVENT_TYPE(7) | EVENT_INDEX(4); in gfx_v8_0_do_edc_gpr_workarounds()5970 amdgpu_ring_write(ring, EVENT_TYPE(VS_PARTIAL_FLUSH) | in gfx_v8_0_ring_emit_vgt_flush()5974 amdgpu_ring_write(ring, EVENT_TYPE(VGT_FLUSH) | in gfx_v8_0_ring_emit_vgt_flush()6058 EVENT_TYPE(CACHE_FLUSH_AND_INV_TS_EVENT) | in gfx_v8_0_ring_emit_fence_gfx()6072 EVENT_TYPE(CACHE_FLUSH_AND_INV_TS_EVENT) | in gfx_v8_0_ring_emit_fence_gfx()6152 EVENT_TYPE(CACHE_FLUSH_AND_INV_TS_EVENT) | in gfx_v8_0_ring_emit_fence_compute()
4777 ib.ptr[ib.length_dw++] = EVENT_TYPE(7) | EVENT_INDEX(4); in gfx_v9_0_do_edc_gpr_workarounds()4805 ib.ptr[ib.length_dw++] = EVENT_TYPE(7) | EVENT_INDEX(4); in gfx_v9_0_do_edc_gpr_workarounds()4833 ib.ptr[ib.length_dw++] = EVENT_TYPE(7) | EVENT_INDEX(4); in gfx_v9_0_do_edc_gpr_workarounds()5604 dw2 |= EOP_TC_WB_ACTION_EN | EVENT_TYPE(CACHE_FLUSH_AND_INV_TS_EVENT) | in gfx_v9_0_ring_emit_fence()5632 amdgpu_ring_write(ring, EVENT_TYPE(event_type) | in gfx_v9_0_ring_emit_event_write()
3000 EVENT_TYPE(CACHE_FLUSH_AND_INV_TS_EVENT) | in gfx_v9_4_3_ring_emit_fence()
1239 #define EVENT_TYPE(x) ((x) << 0) macro
1813 #define EVENT_TYPE(x) ((x) << 0) macro
1664 #define EVENT_TYPE(x) ((x) << 0) macro
1392 radeon_ring_write(ring, EVENT_TYPE(CACHE_FLUSH_AND_INV_EVENT_TS) | EVENT_INDEX(5)); in cayman_fence_ring_emit()
2887 radeon_ring_write(ring, EVENT_TYPE(CACHE_FLUSH_AND_INV_EVENT_TS) | EVENT_INDEX(5)); in r600_fence_ring_emit()2900 radeon_ring_write(ring, EVENT_TYPE(CACHE_FLUSH_AND_INV_EVENT) | EVENT_INDEX(0)); in r600_fence_ring_emit()