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Searched refs:ENABLE_L2_CACHE (Results 1 – 25 of 31) sorted by relevance

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/linux/drivers/gpu/drm/amd/amdgpu/
H A Dgfxhub_v3_0_3.c221 tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL, ENABLE_L2_CACHE, 1); in gfxhub_v3_0_3_init_cache_regs()
392 WREG32_FIELD15_PREREG(GC, 0, GCVM_L2_CNTL, ENABLE_L2_CACHE, 0); in gfxhub_v3_0_3_gart_disable()
H A Dgfxhub_v2_0.c215 tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL, ENABLE_L2_CACHE, 1); in gfxhub_v2_0_init_cache_regs()
381 WREG32_FIELD15(GC, 0, GCVM_L2_CNTL, ENABLE_L2_CACHE, 0); in gfxhub_v2_0_gart_disable()
H A Dgfxhub_v1_0.c180 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_CACHE, 1); in gfxhub_v1_0_init_cache_regs()
366 WREG32_FIELD15(GC, 0, VM_L2_CNTL, ENABLE_L2_CACHE, 0); in gfxhub_v1_0_gart_disable()
H A Dgfxhub_v11_5_0.c219 tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL, ENABLE_L2_CACHE, 1); in gfxhub_v11_5_0_init_cache_regs()
402 WREG32_FIELD15_PREREG(GC, 0, GCVM_L2_CNTL, ENABLE_L2_CACHE, 0); in gfxhub_v11_5_0_gart_disable()
H A Dmmhub_v3_0_2.c234 tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL, ENABLE_L2_CACHE, 1); in mmhub_v3_0_2_init_cache_regs()
410 tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL, ENABLE_L2_CACHE, 0); in mmhub_v3_0_2_gart_disable()
H A Dgfxhub_v3_0.c216 tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL, ENABLE_L2_CACHE, 1); in gfxhub_v3_0_init_cache_regs()
399 WREG32_FIELD15_PREREG(GC, 0, GCVM_L2_CNTL, ENABLE_L2_CACHE, 0); in gfxhub_v3_0_gart_disable()
H A Dgfxhub_v12_0.c224 tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL, ENABLE_L2_CACHE, 1); in gfxhub_v12_0_init_cache_regs()
407 WREG32_FIELD15_PREREG(GC, 0, GCVM_L2_CNTL, ENABLE_L2_CACHE, 0); in gfxhub_v12_0_gart_disable()
H A Dmmhub_v3_0_1.c235 tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL, ENABLE_L2_CACHE, 1); in mmhub_v3_0_1_init_cache_regs()
405 tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL, ENABLE_L2_CACHE, 0); in mmhub_v3_0_1_gart_disable()
H A Dmmhub_v3_0.c242 tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL, ENABLE_L2_CACHE, 1); in mmhub_v3_0_init_cache_regs()
418 tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL, ENABLE_L2_CACHE, 0); in mmhub_v3_0_gart_disable()
H A Dmmhub_v2_3.c210 tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL, ENABLE_L2_CACHE, 1); in mmhub_v2_3_init_cache_regs()
394 tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL, ENABLE_L2_CACHE, 0); in mmhub_v2_3_gart_disable()
H A Dmmhub_v2_0.c286 tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL, ENABLE_L2_CACHE, 1); in mmhub_v2_0_init_cache_regs()
462 tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL, ENABLE_L2_CACHE, 0); in mmhub_v2_0_gart_disable()
H A Dmmhub_v3_3.c231 tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL, ENABLE_L2_CACHE, 1); in mmhub_v3_3_init_cache_regs()
451 tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL, ENABLE_L2_CACHE, 0); in mmhub_v3_3_gart_disable()
H A Dmmhub_v4_1_0.c243 tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL, ENABLE_L2_CACHE, 1); in mmhub_v4_1_0_init_cache_regs()
419 tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL, ENABLE_L2_CACHE, 0); in mmhub_v4_1_0_gart_disable()
H A Dgfxhub_v1_2.c229 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_CACHE, 1); in gfxhub_v1_2_xcc_init_cache_regs()
463 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_CACHE, 0); in gfxhub_v1_2_xcc_gart_disable()
H A Dmmhub_v1_8.c229 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_CACHE, 1); in mmhub_v1_8_init_cache_regs()
456 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_CACHE, in mmhub_v1_8_gart_disable()
H A Dgfxhub_v2_1.c221 tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL, ENABLE_L2_CACHE, 1); in gfxhub_v2_1_init_cache_regs()
407 WREG32_FIELD15(GC, 0, GCVM_L2_CNTL, ENABLE_L2_CACHE, 0); in gfxhub_v2_1_gart_disable()
H A Dmmhub_v1_7.c184 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_CACHE, 1); in mmhub_v1_7_init_cache_regs()
372 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_CACHE, 0); in mmhub_v1_7_gart_disable()
H A Dmmhub_v9_4.c209 ENABLE_L2_CACHE, 1); in mmhub_v9_4_init_cache_regs()
436 ENABLE_L2_CACHE, 0); in mmhub_v9_4_gart_disable()
H A Dsid.h371 #define ENABLE_L2_CACHE (1 << 0) macro
/linux/drivers/gpu/drm/radeon/
H A Drv770.c907 WREG32(VM_L2_CNTL, ENABLE_L2_CACHE | ENABLE_L2_FRAGMENT_PROCESSING | in rv770_pcie_gart_enable()
984 WREG32(VM_L2_CNTL, ENABLE_L2_CACHE | ENABLE_L2_FRAGMENT_PROCESSING | in rv770_agp_enable()
H A Drv770d.h643 #define ENABLE_L2_CACHE (1 << 0) macro
H A Dnid.h105 #define ENABLE_L2_CACHE (1 << 0) macro
H A Dsid.h370 #define ENABLE_L2_CACHE (1 << 0) macro
H A Dcikd.h488 #define ENABLE_L2_CACHE (1 << 0) macro
H A Devergreend.h1151 #define ENABLE_L2_CACHE (1 << 0) macro

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