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Searched refs:ENABLE_L2_CACHE (Results 1 – 21 of 21) sorted by relevance

/linux/drivers/gpu/drm/amd/amdgpu/
H A Dgfxhub_v3_0_3.c221 tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL, ENABLE_L2_CACHE, 1); in gfxhub_v3_0_3_init_cache_regs()
392 WREG32_FIELD15_PREREG(GC, 0, GCVM_L2_CNTL, ENABLE_L2_CACHE, 0); in gfxhub_v3_0_3_gart_disable()
H A Dgfxhub_v2_0.c215 tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL, ENABLE_L2_CACHE, 1); in gfxhub_v2_0_init_cache_regs()
381 WREG32_FIELD15(GC, 0, GCVM_L2_CNTL, ENABLE_L2_CACHE, 0); in gfxhub_v2_0_gart_disable()
H A Dgfxhub_v11_5_0.c219 tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL, ENABLE_L2_CACHE, 1); in gfxhub_v11_5_0_init_cache_regs()
402 WREG32_FIELD15_PREREG(GC, 0, GCVM_L2_CNTL, ENABLE_L2_CACHE, 0); in gfxhub_v11_5_0_gart_disable()
H A Dgfxhub_v3_0.c216 tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL, ENABLE_L2_CACHE, 1); in gfxhub_v3_0_init_cache_regs()
399 WREG32_FIELD15_PREREG(GC, 0, GCVM_L2_CNTL, ENABLE_L2_CACHE, 0); in gfxhub_v3_0_gart_disable()
H A Dgfxhub_v12_0.c224 tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL, ENABLE_L2_CACHE, 1); in gfxhub_v12_0_init_cache_regs()
407 WREG32_FIELD15_PREREG(GC, 0, GCVM_L2_CNTL, ENABLE_L2_CACHE, 0); in gfxhub_v12_0_gart_disable()
H A Dmmhub_v3_0_2.c233 tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL, ENABLE_L2_CACHE, 1); in mmhub_v3_0_2_init_cache_regs()
409 tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL, ENABLE_L2_CACHE, 0); in mmhub_v3_0_2_gart_disable()
H A Dmmhub_v3_0_1.c233 tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL, ENABLE_L2_CACHE, 1); in mmhub_v3_0_1_init_cache_regs()
403 tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL, ENABLE_L2_CACHE, 0); in mmhub_v3_0_1_gart_disable()
H A Dmmhub_v2_3.c201 tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL, ENABLE_L2_CACHE, 1); in mmhub_v2_3_init_cache_regs()
385 tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL, ENABLE_L2_CACHE, 0); in mmhub_v2_3_gart_disable()
H A Dmmhub_v4_1_0.c228 tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL, ENABLE_L2_CACHE, 1); in mmhub_v4_1_0_init_cache_regs()
404 tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL, ENABLE_L2_CACHE, 0); in mmhub_v4_1_0_gart_disable()
H A Dmmhub_v3_0.c234 tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL, ENABLE_L2_CACHE, 1); in mmhub_v3_0_init_cache_regs()
410 tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL, ENABLE_L2_CACHE, 0); in mmhub_v3_0_gart_disable()
H A Dmmhub_v2_0.c271 tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL, ENABLE_L2_CACHE, 1); in mmhub_v2_0_init_cache_regs()
447 tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL, ENABLE_L2_CACHE, 0); in mmhub_v2_0_gart_disable()
H A Dmmhub_v1_0.c166 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_CACHE, 1); in mmhub_v1_0_init_cache_regs()
413 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_CACHE, 0); in mmhub_v1_0_gart_disable()
H A Dmmhub_v4_2_0.c370 tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL, ENABLE_L2_CACHE, 1); in mmhub_v4_2_0_mid_init_cache_regs()
611 tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL, ENABLE_L2_CACHE, 0); in mmhub_v4_2_0_mid_gart_disable()
/linux/drivers/gpu/drm/radeon/
H A Drv770.c907 WREG32(VM_L2_CNTL, ENABLE_L2_CACHE | ENABLE_L2_FRAGMENT_PROCESSING | in rv770_pcie_gart_enable()
984 WREG32(VM_L2_CNTL, ENABLE_L2_CACHE | ENABLE_L2_FRAGMENT_PROCESSING | in rv770_agp_enable()
H A Drv770d.h643 #define ENABLE_L2_CACHE (1 << 0) macro
H A Dnid.h105 #define ENABLE_L2_CACHE (1 << 0) macro
H A Dcikd.h488 #define ENABLE_L2_CACHE (1 << 0) macro
H A Devergreend.h1151 #define ENABLE_L2_CACHE (1 << 0) macro
H A Dr600d.h588 #define ENABLE_L2_CACHE (1 << 0) macro
H A Dni.c1268 WREG32(VM_L2_CNTL, ENABLE_L2_CACHE | in cayman_pcie_gart_enable()
H A Dr600.c1142 WREG32(VM_L2_CNTL, ENABLE_L2_CACHE | ENABLE_L2_FRAGMENT_PROCESSING | in r600_pcie_gart_enable()
1234 WREG32(VM_L2_CNTL, ENABLE_L2_CACHE | ENABLE_L2_FRAGMENT_PROCESSING | in r600_agp_enable()