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Searched refs:ENABLE_L1_TLB (Results 1 – 24 of 24) sorted by relevance

/linux/drivers/gpu/drm/amd/amdgpu/
H A Dgfxhub_v3_0_3.c196 tmp = REG_SET_FIELD(tmp, GCMC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 1); in gfxhub_v3_0_3_init_tlb_regs()
386 tmp = REG_SET_FIELD(tmp, GCMC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 0); in gfxhub_v3_0_3_gart_disable()
H A Dgfxhub_v2_0.c193 tmp = REG_SET_FIELD(tmp, GCMC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 1); in gfxhub_v2_0_init_tlb_regs()
374 tmp = REG_SET_FIELD(tmp, GCMC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 0); in gfxhub_v2_0_gart_disable()
H A Dgfxhub_v11_5_0.c194 tmp = REG_SET_FIELD(tmp, GCMC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 1); in gfxhub_v11_5_0_init_tlb_regs()
396 tmp = REG_SET_FIELD(tmp, GCMC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 0); in gfxhub_v11_5_0_gart_disable()
H A Dmmhub_v3_0_2.c209 tmp = REG_SET_FIELD(tmp, MMMC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 1); in mmhub_v3_0_2_init_tlb_regs()
403 tmp = REG_SET_FIELD(tmp, MMMC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 0); in mmhub_v3_0_2_gart_disable()
H A Dgfxhub_v3_0.c191 tmp = REG_SET_FIELD(tmp, GCMC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 1); in gfxhub_v3_0_init_tlb_regs()
393 tmp = REG_SET_FIELD(tmp, GCMC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 0); in gfxhub_v3_0_gart_disable()
H A Dgfxhub_v12_0.c199 tmp = REG_SET_FIELD(tmp, GCMC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 1); in gfxhub_v12_0_init_tlb_regs()
401 tmp = REG_SET_FIELD(tmp, GCMC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 0); in gfxhub_v12_0_gart_disable()
H A Dmmhub_v3_0_1.c223 tmp = REG_SET_FIELD(tmp, MMMC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 1); in mmhub_v3_0_1_init_tlb_regs()
405 tmp = REG_SET_FIELD(tmp, MMMC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 0); in mmhub_v3_0_1_gart_disable()
H A Dmmhub_v3_0.c217 tmp = REG_SET_FIELD(tmp, MMMC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 1); in mmhub_v3_0_init_tlb_regs()
411 tmp = REG_SET_FIELD(tmp, MMMC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 0); in mmhub_v3_0_gart_disable()
H A Dmmhub_v2_3.c192 tmp = REG_SET_FIELD(tmp, MMMC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 1); in mmhub_v2_3_init_tlb_regs()
387 tmp = REG_SET_FIELD(tmp, MMMC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 0); in mmhub_v2_3_gart_disable()
H A Dmmhub_v2_0.c262 tmp = REG_SET_FIELD(tmp, MMMC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 1); in mmhub_v2_0_init_tlb_regs()
455 tmp = REG_SET_FIELD(tmp, MMMC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 0); in mmhub_v2_0_gart_disable()
H A Dmmhub_v4_1_0.c210 tmp = REG_SET_FIELD(tmp, MMMC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 1); in mmhub_v4_1_0_init_tlb_regs()
404 tmp = REG_SET_FIELD(tmp, MMMC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 0); in mmhub_v4_1_0_gart_disable()
H A Dmmhub_v3_3.c316 tmp = REG_SET_FIELD(tmp, MMMC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 1); in mmhub_v3_3_init_tlb_regs()
548 tmp = REG_SET_FIELD(tmp, MMMC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 0); in mmhub_v3_3_gart_disable()
H A Dmmhub_v1_0.c144 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 1); in mmhub_v1_0_init_tlb_regs()
403 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 0); in mmhub_v1_0_gart_disable()
H A Dgmc_v7_0.c627 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 1); in gmc_v7_0_gart_enable()
747 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 0); in gmc_v7_0_gart_disable()
H A Dgmc_v8_0.c844 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 1); in gmc_v8_0_gart_enable()
981 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 0); in gmc_v8_0_gart_disable()
/linux/drivers/gpu/drm/radeon/
H A Drv770.c913 tmp = ENABLE_L1_TLB | ENABLE_L1_FRAGMENT_PROCESSING | in rv770_pcie_gart_enable()
990 tmp = ENABLE_L1_TLB | ENABLE_L1_FRAGMENT_PROCESSING | in rv770_agp_enable()
H A Drv770d.h465 #define ENABLE_L1_TLB (1 << 0) macro
H A Dnid.h179 #define ENABLE_L1_TLB (1 << 0) macro
H A Dcikd.h600 #define ENABLE_L1_TLB (1 << 0) macro
H A Devergreend.h955 #define ENABLE_L1_TLB (1 << 0) macro
H A Dr600d.h332 #define ENABLE_L1_TLB (1 << 0) macro
H A Dni.c1262 ENABLE_L1_TLB | in cayman_pcie_gart_enable()
H A Dr600.c1148 tmp = ENABLE_L1_TLB | ENABLE_L1_FRAGMENT_PROCESSING | in r600_pcie_gart_enable()
1240 tmp = ENABLE_L1_TLB | ENABLE_L1_FRAGMENT_PROCESSING | in r600_agp_enable()
H A Devergreen.c2419 tmp = ENABLE_L1_TLB | ENABLE_L1_FRAGMENT_PROCESSING | in evergreen_pcie_gart_enable()
2502 tmp = ENABLE_L1_TLB | ENABLE_L1_FRAGMENT_PROCESSING | in evergreen_agp_enable()