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Searched refs:ENABLE_L1_TLB (Results 1 – 16 of 16) sorted by relevance

/linux/drivers/gpu/drm/amd/amdgpu/
H A Dgfxhub_v2_0.c193 tmp = REG_SET_FIELD(tmp, GCMC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 1); in gfxhub_v2_0_init_tlb_regs()
374 tmp = REG_SET_FIELD(tmp, GCMC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 0); in gfxhub_v2_0_gart_disable()
H A Dgfxhub_v1_0.c161 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 1); in gfxhub_v1_0_init_tlb_regs()
358 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 0); in gfxhub_v1_0_gart_disable()
H A Dmmhub_v2_0.c247 tmp = REG_SET_FIELD(tmp, MMMC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 1); in mmhub_v2_0_init_tlb_regs()
440 tmp = REG_SET_FIELD(tmp, MMMC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 0); in mmhub_v2_0_gart_disable()
H A Dmmhub_v2_3.c183 tmp = REG_SET_FIELD(tmp, MMMC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 1); in mmhub_v2_3_init_tlb_regs()
378 tmp = REG_SET_FIELD(tmp, MMMC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 0); in mmhub_v2_3_gart_disable()
H A Dgfxhub_v2_1.c197 tmp = REG_SET_FIELD(tmp, GCMC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 1); in gfxhub_v2_1_init_tlb_regs()
398 tmp = REG_SET_FIELD(tmp, GCMC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 0); in gfxhub_v2_1_gart_disable()
H A Dgfxhub_v1_2.c207 ENABLE_L1_TLB, 1); in gfxhub_v1_2_xcc_init_tlb_regs()
461 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 0); in gfxhub_v1_2_xcc_gart_disable()
H A Dmmhub_v1_0.c144 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 1); in mmhub_v1_0_init_tlb_regs()
403 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 0); in mmhub_v1_0_gart_disable()
H A Dgfxhub_v12_1.c265 ENABLE_L1_TLB, 1); in gfxhub_v12_1_xcc_init_tlb_regs()
560 ENABLE_L1_TLB, 0); in gfxhub_v12_1_xcc_gart_disable()
/linux/drivers/gpu/drm/radeon/
H A Drv770.c913 tmp = ENABLE_L1_TLB | ENABLE_L1_FRAGMENT_PROCESSING | in rv770_pcie_gart_enable()
990 tmp = ENABLE_L1_TLB | ENABLE_L1_FRAGMENT_PROCESSING | in rv770_agp_enable()
H A Drv770d.h465 #define ENABLE_L1_TLB (1 << 0) macro
H A Dnid.h179 #define ENABLE_L1_TLB (1 << 0) macro
H A Dcikd.h600 #define ENABLE_L1_TLB (1 << 0) macro
H A Devergreend.h955 #define ENABLE_L1_TLB (1 << 0) macro
H A Dr600d.h332 #define ENABLE_L1_TLB (1 << 0) macro
H A Dni.c1262 ENABLE_L1_TLB | in cayman_pcie_gart_enable()
H A Dr600.c1148 tmp = ENABLE_L1_TLB | ENABLE_L1_FRAGMENT_PROCESSING | in r600_pcie_gart_enable()
1240 tmp = ENABLE_L1_TLB | ENABLE_L1_FRAGMENT_PROCESSING | in r600_agp_enable()