| /linux/Documentation/devicetree/bindings/clock/ti/ |
| H A D | dpll.txt | 1 Binding for Texas Instruments DPLL clock.
4 register-mapped DPLL with usually two selectable input clocks
10 for the actual DPLL clock.
37 - reg : offsets for the register set for controlling the DPLL.
43 "ssc-deltam" - DPLL supports spread spectrum clocking (SSC), contains
45 "ssc-modfreq" - DPLL supports spread spectrum clocking (SSC), contains
52 - DPLL mode setting - defining any one or more of the following overrides
54 - ti,low-power-stop : DPLL supports low power stop mode, gating output
55 - ti,low-power-bypass : DPLL output matches rate of parent bypass clock
56 - ti,lock : DPLL locks in programmed rate
[all …]
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| H A D | apll.txt | 9 a subtype of a DPLL [2], although a simplified one at that.
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| /linux/drivers/dpll/zl3073x/ |
| H A D | Kconfig | 4 tristate "Microchip Azurite DPLL/PTP/SyncE devices" if COMPILE_TEST
6 select DPLL
10 This driver supports Microchip Azurite family DPLL/PTP/SyncE
11 devices that support up to 5 independent DPLL channels,
23 This is I2C bus implementation for Microchip Azurite DPLL/PTP/SyncE
35 This is SPI bus implementation for Microchip Azurite DPLL/PTP/SyncE
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| /linux/arch/arm64/boot/dts/xilinx/ |
| H A D | xlnx-zynqmp-clk.h | 15 #define DPLL 3 macro
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| /linux/arch/arm/boot/dts/samsung/ |
| H A D | exynos5422-odroid-core.dtsi | 101 /* derived from 600MHz DPLL */
203 /* derived from 600MHz DPLL */
239 /* derived from 600MHz DPLL */
251 /* derived from 600MHz DPLL */
266 /* derived from 600MHz DPLL */
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| /linux/arch/arm/mach-omap2/ |
| H A D | sleep24xx.S | 60 mov r5, #0x2000 @ set delay (DPLL relock + DLL relock)
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| /linux/drivers/gpu/drm/i915/display/ |
| H A D | intel_dvo.c | 461 dpll[pipe] = intel_de_rmw(display, DPLL(display, pipe), 0, in intel_dvo_init_dev()
468 intel_de_write(display, DPLL(display, pipe), dpll[pipe]); in intel_dvo_init_dev()
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| H A D | intel_display_power_well.c | 1299 * CHV DPLL B/C have some issues if VGA mode is enabled. in vlv_display_power_well_deinit()
1302 u32 val = intel_de_read(display, DPLL(display, pipe)); in vlv_display_power_well_deinit()
1308 intel_de_write(display, DPLL(display, pipe), val); in vlv_display_power_well_enable()
1458 (intel_de_read(display, DPLL(display, PIPE_B)) & DPLL_VCO_ENABLE) == 0) in assert_chv_phy_status()
1640 * (eg. for pipe B DPLL) the entire channel will in chv_phy_powergate_ch()
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| H A D | intel_display.c | 1323 * Make sure the DPLL state is up-to-date for fastset TypeC ports after non-blocking commits. in intel_encoders_pre_pll_enable()
1324 * TODO: Update the DPLL state for all cases in the encoder->update_prepare() hook. in intel_encoders_pre_pll_enable()
8423 * the P1/P2 dividers. Otherwise the DPLL will keep using the old in i830_disable_pipe()
8426 intel_de_write(display, DPLL(display, pipe), in i830_disable_pipe()
8428 intel_de_write(display, DPLL(display, pipe), dpll); in i830_disable_pipe()
8431 intel_de_posting_read(display, DPLL(display, pipe)); in intel_scanout_needs_vtd_wa()
8435 * DPLL is enabled and the clocks are stable.
8439 intel_de_write(display, DPLL(display, pipe), dpll);
8443 intel_de_write(display, DPLL(display, pipe), dpll);
8444 intel_de_posting_read(display, DPLL(displa
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| /linux/Documentation/arch/arm/omap/ |
| H A D | dss.rst | 32 - Use DSI DPLL to create DSS FCK
301 Using DSI DPLL to generate pixel clock it is possible produce the pixel clock
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| /linux/Documentation/networking/device_drivers/ethernet/intel/ |
| H A D | ice.rst | 937 There are adapters with DPLL, where pins are connected to the DPLL instead of
940 To see input signal on those PTP pins, you need to configure DPLL properly.
941 Output signal is only visible on DPLL and to send it to the board SMA/U.FL pins,
942 DPLL output pins have to be manually configured.
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| /linux/drivers/net/wireless/realtek/rtlwifi/rtl8192se/ |
| H A D | reg.h | 256 #define DPLL 0x034A macro
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| /linux/drivers/net/ethernet/intel/ |
| H A D | Kconfig | 306 select DPLL
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| /linux/Documentation/networking/device_drivers/hamradio/ |
| H A D | z8530drv.rst | 308 present at all (BayCom). It feeds back the output of the DPLL
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| /linux/ |
| H A D | MAINTAINERS | 7766 DPLL SUBSYSTEM
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