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Searched refs:DPLL (Results 1 – 17 of 17) sorted by relevance

/linux/Documentation/devicetree/bindings/clock/ti/
H A Ddpll.txt1 Binding for Texas Instruments DPLL clock.
4 register-mapped DPLL with usually two selectable input clocks
10 for the actual DPLL clock.
37 - reg : offsets for the register set for controlling the DPLL.
43 "ssc-deltam" - DPLL supports spread spectrum clocking (SSC), contains
45 "ssc-modfreq" - DPLL supports spread spectrum clocking (SSC), contains
52 - DPLL mode setting - defining any one or more of the following overrides
54 - ti,low-power-stop : DPLL supports low power stop mode, gating output
55 - ti,low-power-bypass : DPLL output matches rate of parent bypass clock
56 - ti,lock : DPLL locks in programmed rate
[all …]
H A Dapll.txt9 a subtype of a DPLL [2], although a simplified one at that.
/linux/drivers/dpll/zl3073x/
H A DKconfig4 tristate "Microchip Azurite DPLL/PTP/SyncE devices" if COMPILE_TEST
6 select DPLL
10 This driver supports Microchip Azurite family DPLL/PTP/SyncE
11 devices that support up to 5 independent DPLL channels,
23 This is I2C bus implementation for Microchip Azurite DPLL/PTP/SyncE
35 This is SPI bus implementation for Microchip Azurite DPLL/PTP/SyncE
/linux/drivers/dpll/
H A DKconfig3 # Generic DPLL drivers configuration
6 menu "DPLL device support"
8 config DPLL config
/linux/arch/arm64/boot/dts/xilinx/
H A Dxlnx-zynqmp-clk.h15 #define DPLL 3 macro
/linux/include/dt-bindings/clock/
H A Dxlnx-zynqmp-clk.h22 #define DPLL 3 macro
/linux/arch/arm/mach-omap2/
H A Dsleep24xx.S60 mov r5, #0x2000 @ set delay (DPLL relock + DLL relock)
/linux/arch/arm/boot/dts/samsung/
H A Dexynos5422-odroid-core.dtsi101 /* derived from 600MHz DPLL */
203 /* derived from 600MHz DPLL */
239 /* derived from 600MHz DPLL */
251 /* derived from 600MHz DPLL */
266 /* derived from 600MHz DPLL */
/linux/Documentation/devicetree/bindings/phy/
H A Dti-phy.txt10 "ti,control-phy-pipe3" - if it has DPLL and individual Rx & Tx power control
/linux/Documentation/arch/arm/omap/
H A Ddss.rst32 - Use DSI DPLL to create DSS FCK
301 Using DSI DPLL to generate pixel clock it is possible produce the pixel clock
/linux/Documentation/networking/device_drivers/ethernet/intel/
H A Dice.rst937 There are adapters with DPLL, where pins are connected to the DPLL instead of
940 To see input signal on those PTP pins, you need to configure DPLL properly.
941 Output signal is only visible on DPLL and to send it to the board SMA/U.FL pins,
942 DPLL output pins have to be manually configured.
/linux/drivers/net/wireless/realtek/rtlwifi/rtl8192se/
H A Dreg.h256 #define DPLL 0x034A macro
/linux/drivers/gpu/drm/i915/display/
H A Dintel_display.c8356 intel_de_write(display, DPLL(display, pipe), in i830_enable_pipe()
8358 intel_de_write(display, DPLL(display, pipe), dpll); in i830_enable_pipe()
8361 intel_de_posting_read(display, DPLL(display, pipe)); in i830_enable_pipe()
8369 intel_de_write(display, DPLL(display, pipe), dpll); in i830_enable_pipe()
8373 intel_de_write(display, DPLL(display, pipe), dpll); in i830_enable_pipe()
8374 intel_de_posting_read(display, DPLL(display, pipe)); in i830_enable_pipe()
8407 intel_de_write(display, DPLL(display, pipe), DPLL_VGA_MODE_DIS); in i830_disable_pipe()
8408 intel_de_posting_read(display, DPLL(display, pipe)); in i830_disable_pipe()
/linux/drivers/net/ethernet/intel/
H A DKconfig306 select DPLL
/linux/arch/arm/boot/dts/rockchip/
H A Drk3036.dtsi242 * Fix the emac parent clock is DPLL instead of APLL.
/linux/Documentation/networking/device_drivers/hamradio/
H A Dz8530drv.rst308 present at all (BayCom). It feeds back the output of the DPLL
/linux/
H A DMAINTAINERS7644 DPLL SUBSYSTEM