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Searched refs:DISPLAY_INFO (Results 1 – 14 of 14) sorted by relevance

/linux/drivers/gpu/drm/i915/display/
H A Dintel_display_device.h121 #define HAS_CDCLK_CRAWL(i915) (DISPLAY_INFO(i915)->has_cdclk_crawl)
122 #define HAS_CDCLK_SQUASH(i915) (DISPLAY_INFO(i915)->has_cdclk_squash)
125 #define HAS_DDI(i915) (DISPLAY_INFO(i915)->has_ddi)
129 #define HAS_DP_MST(i915) (DISPLAY_INFO(i915)->has_dp_mst)
132 #define HAS_DSB(i915) (DISPLAY_INFO(i915)->has_dsb)
136 #define HAS_FPGA_DBG_UNCLAIMED(i915) (DISPLAY_INFO(i915)->has_fpga_dbg)
140 #define HAS_GMCH(i915) (DISPLAY_INFO(i915)->has_gmch)
142 #define HAS_IPC(i915) (DISPLAY_INFO(i915)->has_ipc)
148 #define HAS_OVERLAY(i915) (DISPLAY_INFO(i915)->has_overlay)
149 #define HAS_PSR(i915) (DISPLAY_INFO(i915)->has_psr)
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H A Dintel_display_reg_defs.h11 #define DISPLAY_MMIO_BASE(dev_priv) (DISPLAY_INFO(dev_priv)->mmio_offset)
39 #define _MMIO_PIPE2(display, pipe, reg) _MMIO(DISPLAY_INFO(display)->pipe_offsets[(pipe)] - \
40 DISPLAY_INFO(display)->pipe_offsets[PIPE_A] + \
42 #define _MMIO_TRANS2(display, tran, reg) _MMIO(DISPLAY_INFO(display)->trans_offsets[(tran)] - \
43 DISPLAY_INFO(display)->trans_offsets[TRANSCODER_A] + \
45 #define _MMIO_CURSOR2(display, pipe, reg) _MMIO(DISPLAY_INFO(display)->cursor_offsets[(pipe)] - \
46 DISPLAY_INFO(display)->cursor_offsets[PIPE_A] + \
H A Dintel_hti.c18 if (DISPLAY_INFO(display)->has_hti) in intel_hti_init()
H A Dintel_color.c2125 return DISPLAY_INFO(i915)->color.gamma_lut_tests; in intel_gamma_lut_tests()
2132 return DISPLAY_INFO(i915)->color.degamma_lut_tests; in intel_degamma_lut_tests()
2143 return DISPLAY_INFO(i915)->color.gamma_lut_size; in intel_gamma_lut_size()
2150 return DISPLAY_INFO(i915)->color.degamma_lut_size; in intel_degamma_lut_size()
2684 DISPLAY_INFO(i915)->color.degamma_lut_size, in glk_assign_luts()
3225 u32 lut_size = DISPLAY_INFO(dev_priv)->color.gamma_lut_size; in i9xx_read_lut_10()
3276 int i, lut_size = DISPLAY_INFO(dev_priv)->color.gamma_lut_size; in i965_read_lut_10p6()
3328 int i, lut_size = DISPLAY_INFO(dev_priv)->color.degamma_lut_size; in chv_read_cgm_degamma()
3354 int i, lut_size = DISPLAY_INFO(i915)->color.gamma_lut_size; in chv_read_cgm_gamma()
3428 int i, lut_size = DISPLAY_INFO(i915)->color.gamma_lut_size; in ilk_read_lut_10()
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H A Dintel_display_device.c1486 DISPLAY_INFO(i915) = info; in intel_display_device_probe()
1489 &DISPLAY_INFO(i915)->__runtime_defaults, in intel_display_device_probe()
1524 DISPLAY_INFO(i915) = &no_display; in intel_display_device_probe()
H A Dintel_display_driver.c559 intel_display_device_info_print(DISPLAY_INFO(i915), in intel_display_driver_register()
H A Dintel_display_power.c1061 u8 slice_mask = DISPLAY_INFO(dev_priv)->dbuf.slice_mask; in gen9_dbuf_slices_update()
1130 unsigned long abox_regs = DISPLAY_INFO(dev_priv)->abox_mask; in icl_mbus_init()
1584 unsigned long abox_mask = DISPLAY_INFO(dev_priv)->abox_mask; in tgl_bw_buddy_init()
H A Dintel_display.h115 for_each_if(DISPLAY_INFO(__dev_priv)->dbuf.slice_mask & BIT(__slice))
H A Dskl_watermark.c527 return DISPLAY_INFO(i915)->dbuf.size / in intel_dbuf_slice_size()
528 hweight8(DISPLAY_INFO(i915)->dbuf.slice_mask); in intel_dbuf_slice_size()
547 WARN_ON(ddb->end > DISPLAY_INFO(i915)->dbuf.size); in skl_ddb_entry_for_slices()
2557 DISPLAY_INFO(i915)->dbuf.slice_mask, in skl_compute_ddb()
H A Dintel_cursor.c42 if (DISPLAY_INFO(dev_priv)->cursor_needs_physical) in intel_cursor_base()
H A Dintel_modeset_setup.c342 if (DISPLAY_INFO(i915)->color.degamma_lut_size) { in intel_crtc_copy_hw_to_uapi_state()
H A Dintel_atomic_plane.c154 DISPLAY_INFO(i915)->cursor_needs_physical; in intel_plane_needs_physical()
H A Dintel_display_debugfs.c638 intel_display_device_info_print(DISPLAY_INFO(i915), in i915_display_capabilities()
/linux/drivers/gpu/drm/i915/
H A Di915_gpu_error.c2003 memcpy(&error->display_device_info, DISPLAY_INFO(i915), in capture_gen()