1 /* 2 * Copyright 2025 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 #ifndef __SMU_V15_0_H__ 24 #define __SMU_V15_0_H__ 25 26 #include "amdgpu_smu.h" 27 28 #define SMU15_DRIVER_IF_VERSION_INV 0xFFFFFFFF 29 #define SMU15_DRIVER_IF_VERSION_SMU_V15_0 0x7 30 31 32 #define FEATURE_MASK(feature) (1ULL << feature) 33 34 /* MP Apertures */ 35 #define MP0_Public 0x03800000 36 #define MP0_SRAM 0x03900000 37 #define MP1_Public 0x03b00000 38 #define MP1_SRAM 0x03c00004 39 40 /* address block */ 41 #define smnMP1_FIRMWARE_FLAGS 0x3010024 42 #define smnMP1_PUB_CTRL 0x3010d10 43 44 #define SMU15_DRIVER_IF_VERSION_SMU_V15_0_8 0x007D0000 45 46 #define FEATURE_MASK(feature) (1ULL << feature) 47 48 #define MAX_PCIE_CONF 3 49 50 #define SMU15_TOOL_SIZE 0x19000 51 52 #define CTF_OFFSET_EDGE 5 53 #define CTF_OFFSET_HOTSPOT 5 54 #define CTF_OFFSET_MEM 5 55 56 extern const int decoded_link_speed[5]; 57 extern const int decoded_link_width[8]; 58 59 #define DECODE_GEN_SPEED(gen_speed_idx) (decoded_link_speed[gen_speed_idx]) 60 #define DECODE_LANE_WIDTH(lane_width_idx) (decoded_link_width[lane_width_idx]) 61 62 struct smu_15_0_max_sustainable_clocks { 63 uint32_t display_clock; 64 uint32_t phy_clock; 65 uint32_t pixel_clock; 66 uint32_t uclock; 67 uint32_t dcef_clock; 68 uint32_t soc_clock; 69 }; 70 71 struct smu_15_0_dpm_tables { 72 struct smu_dpm_table soc_table; 73 struct smu_dpm_table gfx_table; 74 struct smu_dpm_table uclk_table; 75 struct smu_dpm_table eclk_table; 76 struct smu_dpm_table vclk_table; 77 struct smu_dpm_table dclk_table; 78 struct smu_dpm_table dcef_table; 79 struct smu_dpm_table pixel_table; 80 struct smu_dpm_table display_table; 81 struct smu_dpm_table phy_table; 82 struct smu_dpm_table fclk_table; 83 struct smu_pcie_table pcie_table; 84 struct smu_dpm_table gl2_table; 85 }; 86 87 struct smu_15_0_dpm_context { 88 struct smu_15_0_dpm_tables dpm_tables; 89 uint32_t workload_policy_mask; 90 uint32_t dcef_min_ds_clk; 91 uint64_t caps; 92 uint32_t board_volt; 93 }; 94 95 enum smu_15_0_power_state { 96 smu_15_0_POWER_STATE__D0 = 0, 97 smu_15_0_POWER_STATE__D1, 98 smu_15_0_POWER_STATE__D3, /* Sleep*/ 99 smu_15_0_POWER_STATE__D4, /* Hibernate*/ 100 smu_15_0_POWER_STATE__D5, /* Power off*/ 101 }; 102 103 struct smu_15_0_power_context { 104 uint32_t power_source; 105 uint8_t in_power_limit_boost_mode; 106 enum smu_15_0_power_state power_state; 107 atomic_t throttle_status; 108 }; 109 110 #if defined(SWSMU_CODE_LAYER_L2) || defined(SWSMU_CODE_LAYER_L3) 111 112 int smu_v15_0_init_microcode(struct smu_context *smu); 113 114 void smu_v15_0_fini_microcode(struct smu_context *smu); 115 116 int smu_v15_0_load_microcode(struct smu_context *smu); 117 118 int smu_v15_0_init_smc_tables(struct smu_context *smu); 119 120 int smu_v15_0_fini_smc_tables(struct smu_context *smu); 121 122 int smu_v15_0_init_power(struct smu_context *smu); 123 124 int smu_v15_0_fini_power(struct smu_context *smu); 125 126 int smu_v15_0_check_fw_status(struct smu_context *smu); 127 128 int smu_v15_0_setup_pptable(struct smu_context *smu); 129 130 int smu_v15_0_get_vbios_bootup_values(struct smu_context *smu); 131 132 int smu_v15_0_set_driver_table_location(struct smu_context *smu); 133 134 int smu_v15_0_set_tool_table_location(struct smu_context *smu); 135 136 int smu_v15_0_notify_memory_pool_location(struct smu_context *smu); 137 138 int smu_v15_0_system_features_control(struct smu_context *smu, 139 bool en); 140 141 int smu_v15_0_set_allowed_mask(struct smu_context *smu); 142 143 int smu_v15_0_notify_display_change(struct smu_context *smu); 144 145 int smu_v15_0_get_current_power_limit(struct smu_context *smu, 146 uint32_t *power_limit); 147 148 int smu_v15_0_set_power_limit(struct smu_context *smu, 149 enum smu_ppt_limit_type limit_type, 150 uint32_t limit); 151 152 int smu_v15_0_gfx_off_control(struct smu_context *smu, bool enable); 153 154 int smu_v15_0_register_irq_handler(struct smu_context *smu); 155 156 int smu_v15_0_baco_set_armd3_sequence(struct smu_context *smu, 157 enum smu_baco_seq baco_seq); 158 159 int smu_v15_0_get_bamaco_support(struct smu_context *smu); 160 161 enum smu_baco_state smu_v15_0_baco_get_state(struct smu_context *smu); 162 163 int smu_v15_0_baco_set_state(struct smu_context *smu, enum smu_baco_state state); 164 165 int smu_v15_0_baco_enter(struct smu_context *smu); 166 int smu_v15_0_baco_exit(struct smu_context *smu); 167 168 int smu_v15_0_get_dpm_ultimate_freq(struct smu_context *smu, enum smu_clk_type clk_type, 169 uint32_t *min, uint32_t *max); 170 171 int smu_v15_0_set_soft_freq_limited_range(struct smu_context *smu, enum smu_clk_type clk_type, 172 uint32_t min, uint32_t max, bool automatic); 173 174 int smu_v15_0_set_hard_freq_limited_range(struct smu_context *smu, 175 enum smu_clk_type clk_type, 176 uint32_t min, 177 uint32_t max); 178 179 int smu_v15_0_set_performance_level(struct smu_context *smu, 180 enum amd_dpm_forced_level level); 181 182 int smu_v15_0_set_power_source(struct smu_context *smu, 183 enum smu_power_src_type power_src); 184 185 int smu_v15_0_set_single_dpm_table(struct smu_context *smu, 186 enum smu_clk_type clk_type, 187 struct smu_dpm_table *single_dpm_table); 188 189 int smu_v15_0_gfx_ulv_control(struct smu_context *smu, 190 bool enablement); 191 192 int smu_v15_0_wait_for_event(struct smu_context *smu, enum smu_event_type event, 193 uint64_t event_arg); 194 195 int smu_v15_0_set_vcn_enable(struct smu_context *smu, 196 bool enable, 197 int inst); 198 199 int smu_v15_0_set_jpeg_enable(struct smu_context *smu, 200 bool enable); 201 202 int smu_v15_0_init_pptable_microcode(struct smu_context *smu); 203 204 int smu_v15_0_run_btc(struct smu_context *smu); 205 206 int smu_v15_0_gpo_control(struct smu_context *smu, 207 bool enablement); 208 209 int smu_v15_0_deep_sleep_control(struct smu_context *smu, 210 bool enablement); 211 212 int smu_v15_0_set_gfx_power_up_by_imu(struct smu_context *smu); 213 214 int smu_v15_0_get_pptable_from_firmware(struct smu_context *smu, 215 void **table, 216 uint32_t *size, 217 uint32_t pptable_id); 218 219 int smu_v15_0_od_edit_dpm_table(struct smu_context *smu, 220 enum PP_OD_DPM_TABLE_COMMAND type, 221 long input[], uint32_t size); 222 223 int smu_v15_0_enable_thermal_alert(struct smu_context *smu); 224 225 int smu_v15_0_disable_thermal_alert(struct smu_context *smu); 226 227 #endif 228 #endif 229