| /linux/include/dt-bindings/clock/ |
| H A D | rk3288-cru.h | 88 #define DCLK_VOP1 191 macro
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| H A D | rockchip,rk3528-cru.h | 272 #define DCLK_VOP1 260 macro
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| H A D | rk3399-cru.h | 130 #define DCLK_VOP1 181 macro
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| H A D | rockchip,rk3588-cru.h | 625 #define DCLK_VOP1 610 macro
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| H A D | rk3568-cru.h | 288 #define DCLK_VOP1 224 macro
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| /linux/arch/arm64/boot/dts/rockchip/ |
| H A D | rk3566-radxa-zero-3.dtsi | 516 assigned-clocks = <&cru DCLK_VOP0>, <&cru DCLK_VOP1>;
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| H A D | rk3566-box-demo.dts | 468 assigned-clocks = <&cru DCLK_VOP0>, <&cru DCLK_VOP1>;
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| H A D | rk3566-lubancat-1.dts | 575 assigned-clocks = <&cru DCLK_VOP0>, <&cru DCLK_VOP1>;
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| H A D | rk3568-photonicat.dts | 569 assigned-clocks = <&cru DCLK_VOP0>, <&cru DCLK_VOP1>;
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| H A D | rk3568-nanopi-r5s.dtsi | 591 assigned-clocks = <&cru DCLK_VOP0>, <&cru DCLK_VOP1>;
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| H A D | rk3566-odroid-m1s.dts | 649 assigned-clocks = <&cru DCLK_VOP0>, <&cru DCLK_VOP1>;
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| H A D | rk3568-easepi-r1.dts | 609 assigned-clocks = <&cru DCLK_VOP0>, <&cru DCLK_VOP1>;
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| H A D | rk3568-evb1-v10.dts | 729 assigned-clocks = <&cru DCLK_VOP0>, <&cru PLL_VPLL>, <&cru DCLK_VOP1>;
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| H A D | rk3566-orangepi-3b.dtsi | 669 assigned-clocks = <&cru DCLK_VOP0>, <&cru DCLK_VOP1>;
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| H A D | rk3566-quartz64-b.dts | 731 assigned-clocks = <&cru DCLK_VOP0>, <&cru DCLK_VOP1>;
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| H A D | rk3566-anbernic-rgxx3.dtsi | 705 assigned-clocks = <&cru DCLK_VOP0>, <&cru DCLK_VOP1>;
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| H A D | rk3568-odroid-m1.dts | 729 assigned-clocks = <&cru DCLK_VOP0>, <&cru DCLK_VOP1>;
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| H A D | rk3566-powkiddy-rk2023.dtsi | 840 assigned-clocks = <&cru DCLK_VOP0>, <&cru DCLK_VOP1>;
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| H A D | rk3566-quartz64-a.dts | 830 assigned-clocks = <&cru DCLK_VOP0>, <&cru DCLK_VOP1>;
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| H A D | rk3566-pinetab2.dtsi | 923 assigned-clocks = <&cru DCLK_VOP0>, <&cru DCLK_VOP1>;
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| /linux/drivers/clk/rockchip/ |
| H A D | clk-rk3288.c | 448 COMPOSITE(DCLK_VOP1, "dclk_vop1", mux_pll_src_cpll_gpll_npll_p, 0,
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| H A D | clk-rk3528.c | 857 GATE(DCLK_VOP1, "dclk_vop1", "dclk_vop_src1", CLK_SET_RATE_PARENT,
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| H A D | clk-rk3399.c | 286 MUX(DCLK_VOP1, "dclk_vop1", mux_dclk_vop1_p, CLK_SET_RATE_PARENT,
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| H A D | clk-rk3588.c | 2112 COMPOSITE_NODIV(DCLK_VOP1, "dclk_vop1", dclk_vop1_p,
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