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Searched refs:CRTC (Results 1 – 25 of 26) sorted by relevance

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/linux/drivers/gpu/drm/nouveau/dispnv04/
H A Dcrtc.c60 crtcstate->CRTC[index]); in crtc_wr_cio_state()
69 regp->CRTC[NV_CIO_CRE_CSB] = nv_crtc->saturation = level; in nv_crtc_set_digital_vibrance()
71 regp->CRTC[NV_CIO_CRE_CSB] = 0x80; in nv_crtc_set_digital_vibrance()
72 regp->CRTC[NV_CIO_CRE_5B] = nv_crtc->saturation << 2; in nv_crtc_set_digital_vibrance()
345 regp->CRTC[NV_CIO_CR_HDT_INDEX] = horizTotal; in nv_crtc_mode_set_vga()
346 regp->CRTC[NV_CIO_CR_HDE_INDEX] = horizDisplay; in nv_crtc_mode_set_vga()
347 regp->CRTC[NV_CIO_CR_HBS_INDEX] = horizBlankStart; in nv_crtc_mode_set_vga()
348 regp->CRTC[NV_CIO_CR_HBE_INDEX] = (1 << 7) | in nv_crtc_mode_set_vga()
350 regp->CRTC[NV_CIO_CR_HRS_INDEX] = horizStart; in nv_crtc_mode_set_vga()
351 regp->CRTC[NV_CIO_CR_HRE_INDEX] = XLATE(horizBlankEnd, 5, NV_CIO_CR_HRE_HBE_5) | in nv_crtc_mode_set_vga()
[all …]
H A Dcursor.c34 crtcstate->CRTC[index]); in crtc_wr_cio_state()
45 regp->CRTC[NV_CIO_CRE_HCUR_ADDR0_INDEX] = in nv04_cursor_set_offset()
48 regp->CRTC[NV_CIO_CRE_HCUR_ADDR1_INDEX] = in nv04_cursor_set_offset()
51 regp->CRTC[NV_CIO_CRE_HCUR_ADDR1_INDEX] |= in nv04_cursor_set_offset()
53 regp->CRTC[NV_CIO_CRE_HCUR_ADDR2_INDEX] = offset >> 24; in nv04_cursor_set_offset()
H A Dtvnv04.c112 state->CRTC[NV_CIO_CRE_49] |= 0x10; in nv04_tv_bind()
114 state->CRTC[NV_CIO_CRE_49] &= ~0x10; in nv04_tv_bind()
117 state->CRTC[NV_CIO_CRE_LCD__INDEX]); in nv04_tv_bind()
119 state->CRTC[NV_CIO_CRE_49]); in nv04_tv_bind()
H A Ddisp.h25 uint8_t CRTC[0xa0]; member
H A Ddfp.c109 crtcstate[head].CRTC[NV_CIO_CRE_LCD__INDEX] &= in nv04_dfp_disable()
252 uint8_t *cr_lcd = &crtcstate[head].CRTC[NV_CIO_CRE_LCD__INDEX]; in nv04_dfp_prepare()
253 uint8_t *cr_lcd_oth = &crtcstate[head ^ 1].CRTC[NV_CIO_CRE_LCD__INDEX]; in nv04_dfp_prepare()
H A Dtvnv17.c410 uint8_t *cr_lcd = &nv04_display(dev)->mode_reg.crtc_reg[head].CRTC[ in nv17_tv_prepare()
476 regs->CRTC[NV_CIO_CRE_53] = 0x40; /* FP_HTIMING */ in nv17_tv_mode_set()
477 regs->CRTC[NV_CIO_CRE_54] = 0; /* FP_VTIMING */ in nv17_tv_mode_set()
H A Dhw.h376 &nv04_display(dev)->mode_reg.crtc_reg[head].CRTC[NV_CIO_CRE_HCUR_ADDR1_INDEX]; in nv_show_cursor()
H A Dhw.c382 crtcstate->CRTC[index] = NVReadVgaCrtc(dev, head, index); in rd_cio_state()
389 NVWriteVgaCrtc(dev, head, index, crtcstate->CRTC[index]); in wr_cio_state()
/linux/Documentation/gpu/
H A Dkms-properties.csv59 armada,CRTC,"""CSC_YUV""",ENUM,"{ ""Auto"" , ""CCIR601"", ""CCIR709"" }",CRTC,TBD
60 ,,"""CSC_RGB""",ENUM,"{ ""Auto"", ""Computer system"", ""Studio"" }",CRTC,TBD
70 exynos,CRTC,“mode”,ENUM,"{ ""normal"", ""blank"" }",CRTC,TBD
88 omap,Generic,“zorder”,RANGE,"Min=0, Max=3","CRTC, Plane",TBD
H A Dvc4.rst15 Pixel Valve (DRM CRTC)
19 :doc: VC4 CRTC module
H A Dtegra.rst75 on two outputs don't match. A display controller is modelled as a CRTC in KMS
/linux/Documentation/gpu/amdgpu/display/
H A Dmpo-overview.rst32 CRTC, primary planes are the planes operated upon by CRTC modesetting and
35 CRTC. Cursor planes are the planes operated upon by the cursor IOCTLs
43 * 4 Primary planes (1 per CRTC).
44 * 4 Cursor planes (1 per CRTC).
74 * Planes cannot be placed outside of the CRTC destination rectangle
138 The overlay plane should be the native size of the CRTC. The compositor must
144 The compositor should create a YUV buffer matching the native size of the CRTC.
151 The overlay plane should be the native size of the CRTC. The compositor must
/linux/drivers/usb/misc/sisusbvga/
H A Dsisusb_struct.h74 unsigned char CRTC[0x19]; member
/linux/Documentation/devicetree/bindings/display/armada/
H A Dmarvell,dove-lcd.txt1 Device Tree bindings for Armada DRM CRTC driver
/linux/include/video/
H A Dneomagic.h129 unsigned char CRTC[25]; /* Crtc Controller */ member
/linux/drivers/gpu/drm/amd/display/dc/dce/
H A Ddce_transform.h99 SRI(DCFE_MEM_LIGHT_SLEEP_CNTL, CRTC, id)
103 SRI(DCFE_MEM_PWR_CTRL, CRTC, id), \
104 SRI(DCFE_MEM_PWR_STATUS, CRTC, id)
167 SRI(DCFE_MEM_LIGHT_SLEEP_CNTL, CRTC, id), \
173 SRI(DCFE_MEM_LIGHT_SLEEP_CNTL, CRTC, id)
H A Ddce_ipp.h58 SRI(DCFE_MEM_PWR_CTRL, CRTC, id)
/linux/drivers/gpu/drm/sti/
H A DNOTES47 FB & planes Cursor CRTC Encoders Bridges/Connectors
/linux/drivers/video/fbdev/sis/
H A Dvstruct.h136 unsigned char CRTC[0x19]; member
H A Dinit.c1895 CRTCdata = SiS_Pr->SiS_StandTable[StandTableIndex].CRTC[i]; in SiS_SetCRTCRegs()
1902 CRTCdata = SiS_Pr->SiS_StandTable[StandTableIndex].CRTC[i]; in SiS_SetCRTCRegs()
/linux/drivers/video/fbdev/savage/
H A Dsavagefb.h155 unsigned char CRTC[25]; /* Crtc Controller */ member
/linux/drivers/video/fbdev/matrox/
H A Dmatroxfb_base.h269 unsigned char CRTC[25]; member
/linux/Documentation/fb/
H A Duvesafb.rst118 nocrtc Do not use CRTC timings while setting the video mode. This option
H A Dmatroxfb.rst239 outputs:XYZ set mapping between CRTC and outputs. Each letter can have value
240 of 0 (for no CRTC), 1 (CRTC1) or 2 (CRTC2), and first letter
H A Dviafb.modes3 # These data are based on the CRTC parameters in

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