60 		       crtcstate->CRTC[index]);  in crtc_wr_cio_state()
69 	regp->CRTC[NV_CIO_CRE_CSB] = nv_crtc->saturation = level;  in nv_crtc_set_digital_vibrance()
71 		regp->CRTC[NV_CIO_CRE_CSB] = 0x80;  in nv_crtc_set_digital_vibrance()
72 		regp->CRTC[NV_CIO_CRE_5B] = nv_crtc->saturation << 2;  in nv_crtc_set_digital_vibrance()
345 	regp->CRTC[NV_CIO_CR_HDT_INDEX] = horizTotal;  in nv_crtc_mode_set_vga()
346 	regp->CRTC[NV_CIO_CR_HDE_INDEX] = horizDisplay;  in nv_crtc_mode_set_vga()
347 	regp->CRTC[NV_CIO_CR_HBS_INDEX] = horizBlankStart;  in nv_crtc_mode_set_vga()
348 	regp->CRTC[NV_CIO_CR_HBE_INDEX] = (1 << 7) |  in nv_crtc_mode_set_vga()
350 	regp->CRTC[NV_CIO_CR_HRS_INDEX] = horizStart;  in nv_crtc_mode_set_vga()
351 	regp->CRTC[NV_CIO_CR_HRE_INDEX] = XLATE(horizBlankEnd, 5, NV_CIO_CR_HRE_HBE_5) |  in nv_crtc_mode_set_vga()
353 	regp->CRTC[NV_CIO_CR_VDT_INDEX] = vertTotal;  in nv_crtc_mode_set_vga()
354 	regp->CRTC[NV_CIO_CR_OVL_INDEX] = XLATE(vertStart, 9, NV_CIO_CR_OVL_VRS_9) |  in nv_crtc_mode_set_vga()
362 	regp->CRTC[NV_CIO_CR_RSAL_INDEX] = 0x00;  in nv_crtc_mode_set_vga()
363 …regp->CRTC[NV_CIO_CR_CELL_HT_INDEX] = ((mode->flags & DRM_MODE_FLAG_DBLSCAN) ? MASK(NV_CIO_CR_CELL…  in nv_crtc_mode_set_vga()
366 	regp->CRTC[NV_CIO_CR_CURS_ST_INDEX] = 0x00;  in nv_crtc_mode_set_vga()
367 	regp->CRTC[NV_CIO_CR_CURS_END_INDEX] = 0x00;  in nv_crtc_mode_set_vga()
368 	regp->CRTC[NV_CIO_CR_SA_HI_INDEX] = 0x00;  in nv_crtc_mode_set_vga()
369 	regp->CRTC[NV_CIO_CR_SA_LO_INDEX] = 0x00;  in nv_crtc_mode_set_vga()
370 	regp->CRTC[NV_CIO_CR_TCOFF_HI_INDEX] = 0x00;  in nv_crtc_mode_set_vga()
371 	regp->CRTC[NV_CIO_CR_TCOFF_LO_INDEX] = 0x00;  in nv_crtc_mode_set_vga()
372 	regp->CRTC[NV_CIO_CR_VRS_INDEX] = vertStart;  in nv_crtc_mode_set_vga()
373 	regp->CRTC[NV_CIO_CR_VRE_INDEX] = 1 << 5 | XLATE(vertEnd, 0, NV_CIO_CR_VRE_3_0);  in nv_crtc_mode_set_vga()
374 	regp->CRTC[NV_CIO_CR_VDE_INDEX] = vertDisplay;  in nv_crtc_mode_set_vga()
376 	regp->CRTC[NV_CIO_CR_OFFSET_INDEX] = fb->pitches[0] / 8;  in nv_crtc_mode_set_vga()
377 	regp->CRTC[NV_CIO_CR_ULINE_INDEX] = 0x00;  in nv_crtc_mode_set_vga()
378 	regp->CRTC[NV_CIO_CR_VBS_INDEX] = vertBlankStart;  in nv_crtc_mode_set_vga()
379 	regp->CRTC[NV_CIO_CR_VBE_INDEX] = vertBlankEnd;  in nv_crtc_mode_set_vga()
380 	regp->CRTC[NV_CIO_CR_MODE_INDEX] = 0x43;  in nv_crtc_mode_set_vga()
381 	regp->CRTC[NV_CIO_CR_LCOMP_INDEX] = 0xff;  in nv_crtc_mode_set_vga()
388 	regp->CRTC[NV_CIO_CRE_RPC0_INDEX] =  in nv_crtc_mode_set_vga()
390 	regp->CRTC[NV_CIO_CRE_42] =  in nv_crtc_mode_set_vga()
392 	regp->CRTC[NV_CIO_CRE_RPC1_INDEX] = mode->crtc_hdisplay < 1280 ?  in nv_crtc_mode_set_vga()
394 	regp->CRTC[NV_CIO_CRE_LSR_INDEX] = XLATE(horizBlankEnd, 6, NV_CIO_CRE_LSR_HBE_6) |  in nv_crtc_mode_set_vga()
399 	regp->CRTC[NV_CIO_CRE_HEB__INDEX] = XLATE(horizStart, 8, NV_CIO_CRE_HEB_HRS_8) |  in nv_crtc_mode_set_vga()
403 	regp->CRTC[NV_CIO_CRE_EBR_INDEX] = XLATE(vertBlankStart, 11, NV_CIO_CRE_EBR_VBS_11) |  in nv_crtc_mode_set_vga()
410 		regp->CRTC[NV_CIO_CRE_ILACE__INDEX] = horizTotal;  in nv_crtc_mode_set_vga()
411 		regp->CRTC[NV_CIO_CRE_HEB__INDEX] |= XLATE(horizTotal, 8, NV_CIO_CRE_HEB_ILC_8);  in nv_crtc_mode_set_vga()
413 		regp->CRTC[NV_CIO_CRE_ILACE__INDEX] = 0xff;  /* interlace off */  in nv_crtc_mode_set_vga()
494 	regp->CRTC[NV_CIO_CRE_ENH_INDEX] = savep->CRTC[NV_CIO_CRE_ENH_INDEX] & ~(1<<5);  in nv_crtc_mode_set_regs()
519 	regp->CRTC[NV_CIO_CRE_53] = 0;  in nv_crtc_mode_set_regs()
520 	regp->CRTC[NV_CIO_CRE_54] = 0;  in nv_crtc_mode_set_regs()
524 		regp->CRTC[NV_CIO_CRE_SCRATCH3__INDEX] = 0x11;  in nv_crtc_mode_set_regs()
526 		regp->CRTC[NV_CIO_CRE_SCRATCH3__INDEX] = 0x88;  in nv_crtc_mode_set_regs()
528 		regp->CRTC[NV_CIO_CRE_SCRATCH3__INDEX] = 0x22;  in nv_crtc_mode_set_regs()
532 	regp->CRTC[NV_CIO_CRE_SCRATCH4__INDEX] = savep->CRTC[NV_CIO_CRE_SCRATCH4__INDEX];  in nv_crtc_mode_set_regs()
542 		regp->CRTC[NV_CIO_CRE_4B] = savep->CRTC[NV_CIO_CRE_4B] | 0x80;  in nv_crtc_mode_set_regs()
546 …regp->CRTC[NV_CIO_CRE_TVOUT_LATENCY] = nv04_display(dev)->saved_reg.crtc_reg[0].CRTC[NV_CIO_CRE_TV…  in nv_crtc_mode_set_regs()
548 		regp->CRTC[NV_CIO_CRE_TVOUT_LATENCY] += 4;  in nv_crtc_mode_set_regs()
552 	regp->CRTC[NV_CIO_CRE_59] = off_chip_digital;  in nv_crtc_mode_set_regs()
555 		regp->CRTC[0x9f] = off_chip_digital ? 0x11 : 0x1;  in nv_crtc_mode_set_regs()
574 		regp->CRTC[NV_CIO_CRE_85] = 0xFF;  in nv_crtc_mode_set_regs()
575 		regp->CRTC[NV_CIO_CRE_86] = 0x1;  in nv_crtc_mode_set_regs()
578 	regp->CRTC[NV_CIO_CRE_PIXEL_INDEX] = (fb->format->depth + 1) / 8;  in nv_crtc_mode_set_regs()
581 		regp->CRTC[NV_CIO_CRE_PIXEL_INDEX] |= (1 << 7);  in nv_crtc_mode_set_regs()
687 	crtc_state->CRTC[NV_CIO_CRE_LCD__INDEX] = crtc_saved->CRTC[NV_CIO_CRE_LCD__INDEX];  in nv_crtc_save()
697 	uint8_t saved_cr21 = nv04_display(dev)->saved_reg.crtc_reg[head].CRTC[NV_CIO_CRE_21];  in nv_crtc_restore()
878 	regp->CRTC[NV_CIO_CRE_PIXEL_INDEX] &= ~3;  in nv04_crtc_do_mode_set_base()
879 	regp->CRTC[NV_CIO_CRE_PIXEL_INDEX] |= (drm_fb->format->depth + 1) / 8;  in nv04_crtc_do_mode_set_base()
887 	regp->CRTC[NV_CIO_CR_OFFSET_INDEX] = drm_fb->pitches[0] >> 3;  in nv04_crtc_do_mode_set_base()
888 	regp->CRTC[NV_CIO_CRE_RPC0_INDEX] =  in nv04_crtc_do_mode_set_base()
890 	regp->CRTC[NV_CIO_CRE_42] =  in nv04_crtc_do_mode_set_base()
905 	regp->CRTC[NV_CIO_CRE_FF_INDEX] = arb_burst;  in nv04_crtc_do_mode_set_base()
906 	regp->CRTC[NV_CIO_CRE_FFLWM__INDEX] = arb_lwm & 0xff;  in nv04_crtc_do_mode_set_base()
911 		regp->CRTC[NV_CIO_CRE_47] = arb_lwm >> 8;  in nv04_crtc_do_mode_set_base()