Searched refs:CP_RB0_CNTL (Results 1 – 6 of 6) sorted by relevance
| /linux/drivers/gpu/drm/radeon/ |
| H A D | nid.h | 484 #define CP_RB0_CNTL 0xC104 macro
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| H A D | cikd.h | 1302 #define CP_RB0_CNTL 0xC104 macro
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| H A D | ni.c | 1606 CP_RB0_CNTL, in cayman_cp_resume()
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| /linux/drivers/gpu/drm/amd/amdgpu/ |
| H A D | gfx_v9_0.c | 3408 tmp = REG_SET_FIELD(0, CP_RB0_CNTL, RB_BUFSZ, rb_bufsz); in gfx_v9_0_cp_gfx_resume()
3409 tmp = REG_SET_FIELD(tmp, CP_RB0_CNTL, RB_BLKSZ, rb_bufsz - 2); in gfx_v9_0_cp_gfx_resume()
3411 tmp = REG_SET_FIELD(tmp, CP_RB0_CNTL, BUF_SWAP, 1); in gfx_v9_0_cp_gfx_resume()
3626 /* set up the HQD, this is similar to CP_RB0_CNTL */ in gfx_v9_0_mqd_init()
3741 /* set up the HQD, this is similar to CP_RB0_CNTL */ in gfx_v9_0_kiq_init_register()
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| H A D | gfx_v12_0.c | 2742 tmp = REG_SET_FIELD(0, CP_RB0_CNTL, RB_BUFSZ, rb_bufsz); in gfx_v12_0_cp_gfx_resume()
2743 tmp = REG_SET_FIELD(tmp, CP_RB0_CNTL, RB_BLKSZ, rb_bufsz - 2); in gfx_v12_0_cp_gfx_resume()
3031 /* set up the gfx_hqd_control, similar as CP_RB0_CNTL */ in gfx_v12_0_gfx_mqd_init()
3215 /* set up the HQD, this is similar to CP_RB0_CNTL */ in gfx_v12_0_compute_mqd_init()
3355 /* set up the HQD, this is similar to CP_RB0_CNTL */ in gfx_v12_0_kiq_init_register()
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| H A D | gfx_v11_0.c | 3772 tmp = REG_SET_FIELD(0, CP_RB0_CNTL, RB_BUFSZ, rb_bufsz); in gfx_v11_0_cp_gfx_resume()
3773 tmp = REG_SET_FIELD(tmp, CP_RB0_CNTL, RB_BLKSZ, rb_bufsz - 2); in gfx_v11_0_cp_gfx_resume()
4177 /* set up the gfx_hqd_control, similar as CP_RB0_CNTL */ in gfx_v11_0_gfx_mqd_init()
4363 /* set up the HQD, this is similar to CP_RB0_CNTL */ in gfx_v11_0_compute_mqd_init()
4504 /* set up the HQD, this is similar to CP_RB0_CNTL */ in gfx_v11_0_kiq_init_register()
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