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Searched refs:CP_RB0_CNTL (Results 1 – 12 of 12) sorted by relevance

/linux/drivers/gpu/drm/radeon/
H A Dnid.h484 #define CP_RB0_CNTL 0xC104 macro
H A Dsid.h1246 #define CP_RB0_CNTL 0xC104 macro
H A Dcikd.h1302 #define CP_RB0_CNTL 0xC104 macro
H A Dsi.c3654 WREG32(CP_RB0_CNTL, tmp); in si_cp_resume()
3657 WREG32(CP_RB0_CNTL, tmp | RB_RPTR_WR_ENA); in si_cp_resume()
3673 WREG32(CP_RB0_CNTL, tmp); in si_cp_resume()
H A Dni.c1606 CP_RB0_CNTL, in cayman_cp_resume()
H A Dcik.c4074 WREG32(CP_RB0_CNTL, tmp); in cik_cp_gfx_resume()
4077 WREG32(CP_RB0_CNTL, tmp | RB_RPTR_WR_ENA); in cik_cp_gfx_resume()
4092 WREG32(CP_RB0_CNTL, tmp); in cik_cp_gfx_resume()
/linux/drivers/gpu/drm/amd/amdgpu/
H A Dgfx_v8_0.c4265 tmp = REG_SET_FIELD(0, CP_RB0_CNTL, RB_BUFSZ, rb_bufsz); in gfx_v8_0_cp_gfx_resume()
4266 tmp = REG_SET_FIELD(tmp, CP_RB0_CNTL, RB_BLKSZ, rb_bufsz - 2); in gfx_v8_0_cp_gfx_resume()
4267 tmp = REG_SET_FIELD(tmp, CP_RB0_CNTL, MTYPE, 3); in gfx_v8_0_cp_gfx_resume()
4268 tmp = REG_SET_FIELD(tmp, CP_RB0_CNTL, MIN_IB_AVAILSZ, 1); in gfx_v8_0_cp_gfx_resume()
4270 tmp = REG_SET_FIELD(tmp, CP_RB0_CNTL, BUF_SWAP, 1); in gfx_v8_0_cp_gfx_resume()
H A Dsid.h1274 #define CP_RB0_CNTL 0x3041 macro
H A Dgfx_v9_0.c3376 tmp = REG_SET_FIELD(0, CP_RB0_CNTL, RB_BUFSZ, rb_bufsz); in gfx_v9_0_cp_gfx_resume()
3377 tmp = REG_SET_FIELD(tmp, CP_RB0_CNTL, RB_BLKSZ, rb_bufsz - 2); in gfx_v9_0_cp_gfx_resume()
3379 tmp = REG_SET_FIELD(tmp, CP_RB0_CNTL, BUF_SWAP, 1); in gfx_v9_0_cp_gfx_resume()
H A Dgfx_v12_0.c2637 tmp = REG_SET_FIELD(0, CP_RB0_CNTL, RB_BUFSZ, rb_bufsz); in gfx_v12_0_cp_gfx_resume()
2638 tmp = REG_SET_FIELD(tmp, CP_RB0_CNTL, RB_BLKSZ, rb_bufsz - 2); in gfx_v12_0_cp_gfx_resume()
H A Dgfx_v11_0.c3613 tmp = REG_SET_FIELD(0, CP_RB0_CNTL, RB_BUFSZ, rb_bufsz); in gfx_v11_0_cp_gfx_resume()
3614 tmp = REG_SET_FIELD(tmp, CP_RB0_CNTL, RB_BLKSZ, rb_bufsz - 2); in gfx_v11_0_cp_gfx_resume()
H A Dgfx_v10_0.c6411 tmp = REG_SET_FIELD(0, CP_RB0_CNTL, RB_BUFSZ, rb_bufsz); in gfx_v10_0_cp_gfx_resume()
6412 tmp = REG_SET_FIELD(tmp, CP_RB0_CNTL, RB_BLKSZ, rb_bufsz - 2); in gfx_v10_0_cp_gfx_resume()
6414 tmp = REG_SET_FIELD(tmp, CP_RB0_CNTL, BUF_SWAP, 1); in gfx_v10_0_cp_gfx_resume()