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Searched refs:CP_RB0_CNTL (Results 1 – 8 of 8) sorted by relevance

/linux/drivers/gpu/drm/radeon/
H A Dnid.h484 #define CP_RB0_CNTL 0xC104 macro
H A Dcikd.h1302 #define CP_RB0_CNTL 0xC104 macro
H A Dni.c1606 CP_RB0_CNTL, in cayman_cp_resume()
/linux/drivers/gpu/drm/amd/amdgpu/
H A Dgfx_v8_0.c4256 tmp = REG_SET_FIELD(0, CP_RB0_CNTL, RB_BUFSZ, rb_bufsz); in gfx_v8_0_cp_gfx_resume()
4257 tmp = REG_SET_FIELD(tmp, CP_RB0_CNTL, RB_BLKSZ, rb_bufsz - 2); in gfx_v8_0_cp_gfx_resume()
4258 tmp = REG_SET_FIELD(tmp, CP_RB0_CNTL, MTYPE, 3); in gfx_v8_0_cp_gfx_resume()
4259 tmp = REG_SET_FIELD(tmp, CP_RB0_CNTL, MIN_IB_AVAILSZ, 1); in gfx_v8_0_cp_gfx_resume()
4261 tmp = REG_SET_FIELD(tmp, CP_RB0_CNTL, BUF_SWAP, 1); in gfx_v8_0_cp_gfx_resume()
H A Dgfx_v9_0.c3409 tmp = REG_SET_FIELD(0, CP_RB0_CNTL, RB_BUFSZ, rb_bufsz); in gfx_v9_0_cp_gfx_resume()
3410 tmp = REG_SET_FIELD(tmp, CP_RB0_CNTL, RB_BLKSZ, rb_bufsz - 2); in gfx_v9_0_cp_gfx_resume()
3412 tmp = REG_SET_FIELD(tmp, CP_RB0_CNTL, BUF_SWAP, 1); in gfx_v9_0_cp_gfx_resume()
H A Dgfx_v12_0.c2768 tmp = REG_SET_FIELD(0, CP_RB0_CNTL, RB_BUFSZ, rb_bufsz); in gfx_v12_0_cp_gfx_resume()
2769 tmp = REG_SET_FIELD(tmp, CP_RB0_CNTL, RB_BLKSZ, rb_bufsz - 2); in gfx_v12_0_cp_gfx_resume()
2770 tmp = REG_SET_FIELD(tmp, CP_RB0_CNTL, KMD_QUEUE, 1); in gfx_v12_0_cp_gfx_resume()
3058 /* set up the gfx_hqd_control, similar as CP_RB0_CNTL */ in gfx_v12_0_gfx_mqd_init()
3243 /* set up the HQD, this is similar to CP_RB0_CNTL */ in gfx_v12_0_compute_mqd_init()
3383 /* set up the HQD, this is similar to CP_RB0_CNTL */ in gfx_v12_0_kiq_init_register()
H A Dgfx_v11_0.c3809 tmp = REG_SET_FIELD(0, CP_RB0_CNTL, RB_BUFSZ, rb_bufsz); in gfx_v11_0_cp_gfx_resume()
3810 tmp = REG_SET_FIELD(tmp, CP_RB0_CNTL, RB_BLKSZ, rb_bufsz - 2); in gfx_v11_0_cp_gfx_resume()
3811 tmp = REG_SET_FIELD(tmp, CP_RB0_CNTL, KMD_QUEUE, 1); in gfx_v11_0_cp_gfx_resume()
4215 /* set up the gfx_hqd_control, similar as CP_RB0_CNTL */ in gfx_v11_0_gfx_mqd_init()
4402 /* set up the HQD, this is similar to CP_RB0_CNTL */ in gfx_v11_0_compute_mqd_init()
4543 /* set up the HQD, this is similar to CP_RB0_CNTL */ in gfx_v11_0_kiq_init_register()
H A Dgfx_v10_0.c6530 tmp = REG_SET_FIELD(0, CP_RB0_CNTL, RB_BUFSZ, rb_bufsz); in gfx_v10_0_cp_gfx_resume()
6531 tmp = REG_SET_FIELD(tmp, CP_RB0_CNTL, RB_BLKSZ, rb_bufsz - 2); in gfx_v10_0_cp_gfx_resume()
6533 tmp = REG_SET_FIELD(tmp, CP_RB0_CNTL, BUF_SWAP, 1); in gfx_v10_0_cp_gfx_resume()