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Searched refs:CP_ME_CNTL (Results 1 – 13 of 13) sorted by relevance

/linux/drivers/gpu/drm/amd/amdgpu/
H A Dmes_v11_0.c428 reset_pipe = REG_SET_FIELD(reset_pipe, CP_ME_CNTL, in mes_v11_0_reset_gfx_pipe_mmio()
430 reset_pipe = REG_SET_FIELD(reset_pipe, CP_ME_CNTL, in mes_v11_0_reset_gfx_pipe_mmio()
432 clean_pipe = REG_SET_FIELD(clean_pipe, CP_ME_CNTL, in mes_v11_0_reset_gfx_pipe_mmio()
434 clean_pipe = REG_SET_FIELD(clean_pipe, CP_ME_CNTL, in mes_v11_0_reset_gfx_pipe_mmio()
438 reset_pipe = REG_SET_FIELD(reset_pipe, CP_ME_CNTL, in mes_v11_0_reset_gfx_pipe_mmio()
440 reset_pipe = REG_SET_FIELD(reset_pipe, CP_ME_CNTL, in mes_v11_0_reset_gfx_pipe_mmio()
442 clean_pipe = REG_SET_FIELD(clean_pipe, CP_ME_CNTL, in mes_v11_0_reset_gfx_pipe_mmio()
444 clean_pipe = REG_SET_FIELD(clean_pipe, CP_ME_CNTL, in mes_v11_0_reset_gfx_pipe_mmio()
H A Dmes_v12_0.c443 reset_pipe = REG_SET_FIELD(reset_pipe, CP_ME_CNTL, in mes_v12_0_reset_gfx_pipe_mmio()
445 reset_pipe = REG_SET_FIELD(reset_pipe, CP_ME_CNTL, in mes_v12_0_reset_gfx_pipe_mmio()
447 clean_pipe = REG_SET_FIELD(clean_pipe, CP_ME_CNTL, in mes_v12_0_reset_gfx_pipe_mmio()
449 clean_pipe = REG_SET_FIELD(clean_pipe, CP_ME_CNTL, in mes_v12_0_reset_gfx_pipe_mmio()
453 reset_pipe = REG_SET_FIELD(reset_pipe, CP_ME_CNTL, in mes_v12_0_reset_gfx_pipe_mmio()
455 reset_pipe = REG_SET_FIELD(reset_pipe, CP_ME_CNTL, in mes_v12_0_reset_gfx_pipe_mmio()
457 clean_pipe = REG_SET_FIELD(clean_pipe, CP_ME_CNTL, in mes_v12_0_reset_gfx_pipe_mmio()
459 clean_pipe = REG_SET_FIELD(clean_pipe, CP_ME_CNTL, in mes_v12_0_reset_gfx_pipe_mmio()
H A Dgfx_v11_0.c2758 * Program CP_ME_CNTL to reset given PIPE to take in gfx_v11_0_config_pfp_cache_rs64()
2763 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, in gfx_v11_0_config_pfp_cache_rs64()
2766 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, in gfx_v11_0_config_pfp_cache_rs64()
2772 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, in gfx_v11_0_config_pfp_cache_rs64()
2775 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, in gfx_v11_0_config_pfp_cache_rs64()
2881 * Program CP_ME_CNTL to reset given PIPE to take in gfx_v11_0_config_me_cache_rs64()
2886 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, in gfx_v11_0_config_me_cache_rs64()
2889 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, in gfx_v11_0_config_me_cache_rs64()
2895 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, in gfx_v11_0_config_me_cache_rs64()
2898 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, in gfx_v11_0_config_me_cache_rs64()
[all...]
H A Dgfx_v12_0.c2169 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, PFP_PIPE0_RESET, 1); in gfx_v12_0_config_gfx_rs64()
2170 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, PFP_PIPE1_RESET, 1); in gfx_v12_0_config_gfx_rs64()
2174 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, PFP_PIPE0_RESET, 0); in gfx_v12_0_config_gfx_rs64()
2175 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, PFP_PIPE1_RESET, 0); in gfx_v12_0_config_gfx_rs64()
2191 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, ME_PIPE0_RESET, 1); in gfx_v12_0_config_gfx_rs64()
2192 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, ME_PIPE1_RESET, 1); in gfx_v12_0_config_gfx_rs64()
2196 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, ME_PIPE0_RESET, 0); in gfx_v12_0_config_gfx_rs64()
2197 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, ME_PIPE1_RESET, 0); in gfx_v12_0_config_gfx_rs64()
2244 * Program CP_ME_CNTL to reset given PIPE to take in gfx_v12_0_set_pfp_ucode_start_addr()
2249 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, in gfx_v12_0_set_pfp_ucode_start_addr()
[all...]
H A Dgfx_v9_0.c3250 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, CE_INVALIDATE_ICACHE, enable ? 0 : 1); in gfx_v9_0_cp_gfx_enable()
3251 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, PFP_INVALIDATE_ICACHE, enable ? 0 : 1); in gfx_v9_0_cp_gfx_enable()
3252 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, ME_INVALIDATE_ICACHE, enable ? 0 : 1); in gfx_v9_0_cp_gfx_enable()
3253 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, CE_PIPE0_RESET, enable ? 0 : 1); in gfx_v9_0_cp_gfx_enable()
3254 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, CE_PIPE1_RESET, enable ? 0 : 1); in gfx_v9_0_cp_gfx_enable()
3255 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, PFP_PIPE0_RESET, enable ? 0 : 1); in gfx_v9_0_cp_gfx_enable()
3256 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, PFP_PIPE1_RESET, enable ? 0 : 1); in gfx_v9_0_cp_gfx_enable()
3257 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, ME_PIPE0_RESET, enable ? 0 : 1); in gfx_v9_0_cp_gfx_enable()
3258 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, ME_PIPE1_RESET, enable ? 0 : 1); in gfx_v9_0_cp_gfx_enable()
3259 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, ME_HALT, enable ? 0 : 1); in gfx_v9_0_cp_gfx_enable()
[all …]
H A Dgfx_v8_0.c4102 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, ME_HALT, 0); in gfx_v8_0_cp_gfx_enable()
4103 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, PFP_HALT, 0); in gfx_v8_0_cp_gfx_enable()
4104 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, CE_HALT, 0); in gfx_v8_0_cp_gfx_enable()
4106 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, ME_HALT, 1); in gfx_v8_0_cp_gfx_enable()
4107 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, PFP_HALT, 1); in gfx_v8_0_cp_gfx_enable()
4108 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, CE_HALT, 1); in gfx_v8_0_cp_gfx_enable()
H A Dgfx_v10_0.c6088 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, ME_HALT, enable ? 0 : 1); in gfx_v10_0_cp_gfx_enable()
6089 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, PFP_HALT, enable ? 0 : 1); in gfx_v10_0_cp_gfx_enable()
6090 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, CE_HALT, enable ? 0 : 1); in gfx_v10_0_cp_gfx_enable()
/linux/drivers/gpu/drm/radeon/
H A Dni.c1438 WREG32(CP_ME_CNTL, 0); in cayman_cp_enable()
1442 WREG32(CP_ME_CNTL, (CP_ME_HALT | CP_PFP_HALT)); in cayman_cp_enable()
1820 WREG32(CP_ME_CNTL, CP_ME_HALT | CP_PFP_HALT); in cayman_gpu_soft_reset()
H A Drv770d.h335 #define CP_ME_CNTL 0x86D8 macro
H A Dnid.h318 #define CP_ME_CNTL 0x86D8 macro
H A Dcikd.h1108 #define CP_ME_CNTL 0x86D8 macro
H A Drv770.c1084 WREG32(CP_ME_CNTL, (CP_ME_HALT | CP_PFP_HALT)); in r700_cp_stop()
H A Devergreend.h461 #define CP_ME_CNTL 0x86D8 macro