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Searched refs:CP_ME_CNTL (Results 1 – 7 of 7) sorted by relevance

/linux/drivers/gpu/drm/amd/amdgpu/
H A Dgfx_v9_0.c3250 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, CE_INVALIDATE_ICACHE, enable ? 0 : 1); in gfx_v9_0_cp_gfx_enable()
3251 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, PFP_INVALIDATE_ICACHE, enable ? 0 : 1); in gfx_v9_0_cp_gfx_enable()
3252 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, ME_INVALIDATE_ICACHE, enable ? 0 : 1); in gfx_v9_0_cp_gfx_enable()
3253 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, CE_PIPE0_RESET, enable ? 0 : 1); in gfx_v9_0_cp_gfx_enable()
3254 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, CE_PIPE1_RESET, enable ? 0 : 1); in gfx_v9_0_cp_gfx_enable()
3255 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, PFP_PIPE0_RESET, enable ? 0 : 1); in gfx_v9_0_cp_gfx_enable()
3256 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, PFP_PIPE1_RESET, enable ? 0 : 1); in gfx_v9_0_cp_gfx_enable()
3257 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, ME_PIPE0_RESET, enable ? 0 : 1); in gfx_v9_0_cp_gfx_enable()
3258 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, ME_PIPE1_RESET, enable ? 0 : 1); in gfx_v9_0_cp_gfx_enable()
3259 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, ME_HALT, enable ? 0 : 1); in gfx_v9_0_cp_gfx_enable()
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/linux/drivers/gpu/drm/radeon/
H A Dni.c1438 WREG32(CP_ME_CNTL, 0); in cayman_cp_enable()
1442 WREG32(CP_ME_CNTL, (CP_ME_HALT | CP_PFP_HALT)); in cayman_cp_enable()
1820 WREG32(CP_ME_CNTL, CP_ME_HALT | CP_PFP_HALT); in cayman_gpu_soft_reset()
H A Drv770d.h335 #define CP_ME_CNTL 0x86D8 macro
H A Dnid.h318 #define CP_ME_CNTL 0x86D8 macro
H A Dcikd.h1108 #define CP_ME_CNTL 0x86D8 macro
H A Drv770.c1084 WREG32(CP_ME_CNTL, (CP_ME_HALT | CP_PFP_HALT)); in r700_cp_stop()
H A Devergreend.h461 #define CP_ME_CNTL 0x86D8 macro