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Searched refs:CP_HQD_PQ_CONTROL__PRIV_STATE__SHIFT (Results 1 – 18 of 18) sorted by relevance

/linux/drivers/gpu/drm/amd/amdkfd/
H A Dkfd_mqd_manager_v9.c507 m->cp_hqd_pq_control |= 1 << CP_HQD_PQ_CONTROL__PRIV_STATE__SHIFT | in init_mqd_hiq()
633 1 << CP_HQD_PQ_CONTROL__PRIV_STATE__SHIFT | in init_mqd_hiq_v9_4_3()
H A Dkfd_mqd_manager_vi.c344 m->cp_hqd_pq_control |= 1 << CP_HQD_PQ_CONTROL__PRIV_STATE__SHIFT | in init_mqd_hiq()
H A Dkfd_mqd_manager_v12.c301 m->cp_hqd_pq_control |= 1 << CP_HQD_PQ_CONTROL__PRIV_STATE__SHIFT | in init_mqd_hiq()
H A Dkfd_mqd_manager_v10.c332 m->cp_hqd_pq_control |= 1 << CP_HQD_PQ_CONTROL__PRIV_STATE__SHIFT | in init_mqd_hiq()
H A Dkfd_mqd_manager_v11.c402 m->cp_hqd_pq_control |= 1 << CP_HQD_PQ_CONTROL__PRIV_STATE__SHIFT | in init_mqd_hiq()
H A Dkfd_mqd_manager_v12_1.c376 m->cp_hqd_pq_control |= 1 << CP_HQD_PQ_CONTROL__PRIV_STATE__SHIFT | in init_mqd_hiq()
/linux/drivers/gpu/drm/amd/include/asic_reg/gca/
H A Dgfx_7_2_sh_mask.h3360 #define CP_HQD_PQ_CONTROL__PRIV_STATE__SHIFT 0x1e macro
H A Dgfx_8_1_sh_mask.h4498 #define CP_HQD_PQ_CONTROL__PRIV_STATE__SHIFT 0x1e macro
H A Dgfx_8_0_sh_mask.h3976 #define CP_HQD_PQ_CONTROL__PRIV_STATE__SHIFT 0x1e macro
/linux/drivers/gpu/drm/amd/include/asic_reg/gc/
H A Dgc_9_0_sh_mask.h12905 #define CP_HQD_PQ_CONTROL__PRIV_STATE__SHIFT … macro
H A Dgc_9_1_sh_mask.h14205 #define CP_HQD_PQ_CONTROL__PRIV_STATE__SHIFT … macro
H A Dgc_9_2_1_sh_mask.h14070 #define CP_HQD_PQ_CONTROL__PRIV_STATE__SHIFT … macro
H A Dgc_9_4_2_sh_mask.h4002 #define CP_HQD_PQ_CONTROL__PRIV_STATE__SHIFT … macro
H A Dgc_11_5_0_sh_mask.h14076 #define CP_HQD_PQ_CONTROL__PRIV_STATE__SHIFT … macro
H A Dgc_11_0_0_sh_mask.h17382 #define CP_HQD_PQ_CONTROL__PRIV_STATE__SHIFT … macro
H A Dgc_12_0_0_sh_mask.h13281 #define CP_HQD_PQ_CONTROL__PRIV_STATE__SHIFT … macro
H A Dgc_10_1_0_sh_mask.h20316 #define CP_HQD_PQ_CONTROL__PRIV_STATE__SHIFT … macro
H A Dgc_11_0_3_sh_mask.h19621 #define CP_HQD_PQ_CONTROL__PRIV_STATE__SHIFT … macro