| /linux/include/dt-bindings/clock/ |
| H A D | exynos5410.h | 37 #define CLK_UART1 258 macro
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| H A D | actions,s500-cmu.h | 59 #define CLK_UART1 39 macro
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| H A D | actions,s700-cmu.h | 59 #define CLK_UART1 37 macro
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| H A D | actions,s900-cmu.h | 86 #define CLK_UART1 68 macro
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| H A D | pistachio-clk.h | 40 #define CLK_UART1 49 macro
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| H A D | exynos5250.h | 94 #define CLK_UART1 290 macro
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| H A D | sophgo,cv1800.h | 90 #define CLK_UART1 79 macro
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| H A D | s5pv210.h | 160 #define CLK_UART1 142 macro
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| H A D | exynos4.h | 151 #define CLK_UART1 313 macro
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| H A D | exynos5420.h | 67 #define CLK_UART1 258 macro
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| H A D | exynos3250.h | 221 #define CLK_UART1 215 macro
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| H A D | sprd,ums512-clk.h | 140 #define CLK_UART1 12 macro
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| H A D | sprd,sc9860-clk.h | 86 #define CLK_UART1 3 macro
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| H A D | rockchip,rk3528-cru.h | 405 #define CLK_UART1 393 macro
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| H A D | rockchip,rk3588-cru.h | 185 #define CLK_UART1 170 macro
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| /linux/drivers/clk/pistachio/ |
| H A D | clk-pistachio.c | 36 GATE(CLK_UART1, "uart1", "uart1_div", 0x104, 17),
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| /linux/arch/arm64/boot/dts/actions/ |
| H A D | s700.dtsi | 127 clocks = <&cmu CLK_UART1>;
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| H A D | s900.dtsi | 133 clocks = <&cmu CLK_UART1>;
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| /linux/arch/arm/boot/dts/samsung/ |
| H A D | s5pv210.dtsi | 333 clocks = <&clocks CLK_UART1>, <&clocks CLK_UART1>,
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| /linux/arch/arm64/boot/dts/sprd/ |
| H A D | whale2.dtsi | 108 <&ap_clk CLK_UART1>,
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| /linux/arch/arm/boot/dts/actions/ |
| H A D | owl-s500.dtsi | 144 clocks = <&cmu CLK_UART1>;
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| /linux/drivers/clk/actions/ |
| H A D | owl-s500.c | 490 [CLK_UART1] = &uart1_clk.common.hw,
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| H A D | owl-s700.c | 529 [CLK_UART1] = &clk_uart1.common.hw,
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| /linux/arch/riscv/boot/dts/sophgo/ |
| H A D | cv180x.dtsi | 307 clocks = <&clk CLK_UART1>, <&clk CLK_APB_UART1>;
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| /linux/drivers/clk/sophgo/ |
| H A D | clk-cv1800.c | 1108 [CLK_UART1] = &clk_uart1.common.hw,
1339 [CLK_UART1] = &clk_uart1.common.hw,
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