| /linux/drivers/clk/mediatek/ |
| H A D | clk-mt6765-mm.c | 33 GATE_MM(CLK_MM_DISP_OVL0, "mm_disp_ovl0", "mm_ck", 7),
|
| H A D | clk-mt8186-mm.c | 35 GATE_MM0(CLK_MM_DISP_OVL0, "mm_disp_ovl0", "top_disp", 2),
|
| H A D | clk-mt8167-mm.c | 48 GATE_MM0(CLK_MM_DISP_OVL0, "mm_disp_ovl0", "smi_mm", 10),
|
| H A D | clk-mt6795-mm.c | 49 GATE_MM0(CLK_MM_DISP_OVL0, "mm_disp_ovl0", "mm_sel", 16),
|
| H A D | clk-mt6797-mm.c | 48 GATE_MM0(CLK_MM_DISP_OVL0, "mm_disp_ovl0", "mm_sel", 15),
|
| H A D | clk-mt8183-mm.c | 56 GATE_MM0(CLK_MM_DISP_OVL0, "mm_disp_ovl0", "mm_sel", 20),
|
| H A D | clk-mt8192-mm.c | 45 GATE_MM0(CLK_MM_DISP_OVL0, "mm_disp_ovl0", "disp_sel", 2),
|
| H A D | clk-mt6779-mm.c | 56 GATE_MM0(CLK_MM_DISP_OVL0, "mm_disp_ovl0", "mm_sel", 20),
|
| H A D | clk-mt8173-mm.c | 52 GATE_MM0(CLK_MM_DISP_OVL0, "mm_disp_ovl0", "mm_sel", 16),
|
| H A D | clk-mt2712-mm.c | 60 GATE_MM0(CLK_MM_DISP_OVL0, "mm_disp_ovl0", "mm_sel", 16),
|
| /linux/include/dt-bindings/clock/ |
| H A D | mt8167-clk.h | 89 #define CLK_MM_DISP_OVL0 10 macro
|
| H A D | mt6797-clk.h | 230 #define CLK_MM_DISP_OVL0 16 macro
|
| H A D | mediatek,mt6795-clk.h | 235 #define CLK_MM_DISP_OVL0 16 macro
|
| H A D | mt8173-clk.h | 263 #define CLK_MM_DISP_OVL0 16 macro
|
| H A D | mt6765-clk.h | 258 #define CLK_MM_DISP_OVL0 7 macro
|
| H A D | mt6779-clk.h | 360 #define CLK_MM_DISP_OVL0 20 macro
|
| H A D | mt8183-clk.h | 328 #define CLK_MM_DISP_OVL0 19 macro
|
| H A D | mt2712-clk.h | 317 #define CLK_MM_DISP_OVL0 16 macro
|
| H A D | mt8186-clk.h | 303 #define CLK_MM_DISP_OVL0 2 macro
|
| H A D | mt8192-clk.h | 426 #define CLK_MM_DISP_OVL0 2 macro
|
| /linux/arch/arm64/boot/dts/mediatek/ |
| H A D | mt6795.dtsi | 737 clocks = <&mmsys CLK_MM_DISP_OVL0>;
|
| H A D | mt8173.dtsi | 1079 clocks = <&mmsys CLK_MM_DISP_OVL0>;
|
| H A D | mt8183.dtsi | 1732 clocks = <&mmsys CLK_MM_DISP_OVL0>;
|
| H A D | mt8192.dtsi | 1508 clocks = <&mmsys CLK_MM_DISP_OVL0>;
|
| H A D | mt8186.dtsi | 1818 clocks = <&mmsys CLK_MM_DISP_OVL0>;
|